Figure 352. Rs232 Cts Flow Control - ST STM32G0 1 Series Reference Manual

Low-power universal asynchronous receiver transmitter (LPUART)
RS232 CTS flow control
If the CTS flow control is enabled (CTSE = 1), then the transmitter checks the nCTS input
before transmitting the next frame. If nCTS is asserted (tied low), then the next data is
transmitted (assuming that data is to be transmitted, in other words, if TXE/TXFE = 0), else
the transmission does not occur. When nCTS is deasserted during a transmission, the
current transmission is completed before the transmitter stops.
When CTSE = 1, the CTSIF status bit is automatically set by hardware as soon as the nCTS
input toggles. It indicates when the receiver becomes ready or not ready for communication.
An interrupt is generated if the CTSIE bit in the LPUART_CR3 register is set.
shows an example of communication with CTS flow control enabled.
nCTS
Transmit data register
TDR
TX
Note: For correct behavior, nCTS must be asserted at least 3 LPUART clock source periods
before the end of the current character. In addition it should be noted that the CTSCF flag
may not be set for pulses shorter than 2 x PCLK periods.
RS485 driver enable
The driver enable feature is enabled by setting bit DEM in the LPUART_CR3 control
register. This enables activating the external transceiver control, through the DE (Driver
Enable) signal. The assertion time is the time between the activation of the DE signal and
the beginning of the start bit. It is programmed using the DEAT [4:0] bitfields in the
LPUART_CR1 control register. The deassertion time is the time between the end of the last
stop bit, in a transmitted message, and the de-activation of the DE signal. It is programmed
using the DEDT [4:0] bitfields in the LPUART_CR1 control register. The polarity of the DE
signal can be configured using the DEP bit in the LPUART_CR3 control register.
1108/1390

Figure 352. RS232 CTS flow control

Data 2 empty
Stop
Start
Data 1
bit
bit
Writing data 3 in TDR
RM0444 Rev 5
CTS
Data 3
Stop
Data 2
bit
Transmission of Data 3 is
delayed until nCTS = 0
RM0444
Figure 352
CTS
empty
Start
Idle
Data 3
bit
MSv31167V1