Tim15 Dma/Interrupt Enable Register (Tim15_Dier); Table 126. Timx Internal Trigger Connection - ST STM32G0 1 Series Reference Manual

RM0444
Bits 16, 2, 1, 0 SMS[3:0]: Slave mode selection
When external signals are selected the active edge of the trigger signal (TRGI) is linked to
the polarity selected on the external input (see Input Control register and Control Register
description.
0000: Slave mode disabled - if CEN = '1' then the prescaler is clocked directly by the
0001: Reserved
0010: Reserved
0011: Reserved
0100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter
0101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The
0110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not
0111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
1000: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI)
Other codes: reserved.
Note: The gated mode must not be used if TI1F_ED is selected as the trigger input
Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2
Slave TIM
TIM15
25.5.4

TIM15 DMA/interrupt enable register (TIM15_DIER)

Address offset: 0x0C
Reset value: 0x0000
15 14 13
COMD
Res. TDE Res.
E
rw rw
Bit 15 Reserved, must be kept at reset value.
Bit 14 TDE: Trigger DMA request enable
0: Trigger DMA request disabled
1: Trigger DMA request enabled
Bit 13 COMDE: COM DMA request enable
0: COM DMA request disabled
1: COM DMA request enabled
internal clock.
and generates an update of the registers.
counter stops (but is not reset) as soon as the trigger becomes low. Both start and
stop of the counter are controlled.
reset). Only the start of the counter is controlled.
reinitializes the counter, generates an update of the registers and starts the counter.
(TS='00100'). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas
the gated mode checks the level of the trigger signal.
signals must be enabled prior to receive events from the master timer, and the clock
frequency (prescaler) must not be changed on-the-fly while triggers are received from
the master timer.

Table 126. TIMx Internal trigger connection

ITR0 (TS = 00000)
TIM2
12 11 10 9
Res. CC2DE CC1DE
rw rw
General-purpose timers (TIM15/TIM16/TIM17)
ITR1 (TS = 00001)
TIM3
8 7 6
UDE BIE TIE COMIE
rw rw rw
RM0444 Rev 5
ITR2 (TS = 00010) ITR3 (TS = 00011)
TIM16_OC1
5 4 3 2
Res. Res. CC2IE
rw rw
TIM17_OC1
1 0
CC1IE UIE
rw rw
785/1390
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