Flash Ecc Register 2 (Flash_Eccr2) - ST STM32G0 1 Series Reference Manual

RM0444
3.7.7

FLASH ECC register 2 (FLASH_ECCR2)

Address offset: 0x01C
Reset value: 0x0000 0000
Access: no wait state when no Flash memory operation is on going, word, half-word and
byte access
This register applies to Bank 2 of dual-bank products.
31 30 29
ECCD ECCC Res. Res.
rc_w1 rc_w1
15 14 13
Res. Res.
r
Bit 31 ECCD: ECC detection
Bit 30 ECCC: ECC correction
Bits 29:25 Reserved, must be kept at reset value.
Bit 24 ECCCIE: ECC correction interrupt enable
Bits 23:21 Reserved, must be kept at reset value.
Bit 20 SYSF_ECC: System Flash memory ECC fail
Bits 19:14 Reserved, must be kept at reset value.
Bits 13:0 ADDR_ECC[13:0]: ECC fail double-word address offset
28 27 26 25
Res. Res. Res.
12 11 10 9
r r r r
Set by hardware when two ECC errors have been detected. When this bit is set, a NMI is
generated.
Cleared by writing 1.
Set by hardware when one ECC error has been detected and corrected. An interrupt is
generated if ECCIE is set.
Cleared by writing 1.
0: ECCC interrupt disabled
1: ECCC interrupt enabled
This bit indicates that the ECC error correction or double ECC error detection is located in
the system Flash memory.
In case of ECC error or ECC correction detected, this bitfield contains double-word offset
(multiple of 64 bits) to Main Flash memory.
24 23 22
ECCCIE Res. Res.
rw
8 7 6
ADDR_ECC[13:0]
r r r
RM0444 Rev 5
Embedded Flash memory (FLASH)
21 20 19 18
SYSF_
Res. Res. Res.
ECC
r
5 4 3 2
r r r r
17 16
Res. Res.
1 0
r r
107/1390
118