Dbg Apb Freeze Register 2 (Dbg_Apb_Fz2) - ST STM32G0 1 Series Reference Manual

Debug support (DBG)
Bit 12 DBG_IWDG_STOP: Clocking of IWDG counter when the core is halted
This bit enables/disables the clock to the counter of IWDG when the core is halted:
0: Enable
1: Disable
Bit 11 DBG_WWDG_STOP: Clocking of WWDG counter when the core is halted
This bit enables/disables the clock to the counter of WWDG when the core is halted:
0: Enable
1: Disable
Bit 10 DBG_RTC_STOP: Clocking of RTC counter when the core is halted
This bit enables/disables the clock to the counter of RTC when the core is halted:
0: Enable
1: Disable
Bits 9:6 Reserved, must be kept at reset value.
Bit 5 DBG_TIM7_STOP: Clocking of TIM7 counter when the core is halted.
This bit enables/disables the clock to the counter of ITIM7 when the core is halted:
0: Enable
1: Disable
Bit 4 DBG_TIM6_STOP: Clocking of TIM6 counter when the core is halted
This bit enables/disables the clock to the counter of TIM6 when the core is halted:
0: Enable
1: Disable
Bits 3:3 Reserved, must be kept at reset value.
Bit 2 DBG_TIM4_STOP: Clocking of TIM4 counter when the core is halted
This bit enables/disables the clock to the counter of TIM4 when the core is halted:
0: Enable
1: Disable
Bit 1 DBG_TIM3_STOP: Clocking of TIM3 counter when the core is halted
This bit enables/disables the clock to the counter of TIM3 when the core is halted:
0: Enable
1: Disable
Bit 0 DBG_TIM2_STOP: Clocking of TIM2 counter when the core is halted
This bit enables/disables the clock to the counter of TIM2 when the core is halted:
0: Enable
1: Disable
40.10.4

DBG APB freeze register 2 (DBG_APB_FZ2)

This register configures the clocking of timer counters when the MCU is under debug.
It is asynchronously reset by the POR (and not the system reset). It can be written by the
debugger under system reset.
Address offset: 0x0C
POR: 0x0000 0000 (not reset by system reset)
Only 32-bit access is supported.
1376/1390 RM0444 Rev 5
RM0444