Capture/Compare Channels; Figure 230. Control Circuit In Normal Mode, Internal Clock Divided By 1; Figure 231. Capture/Compare Channel (Example: Channel 1 Input Stage) - ST STM32G0 1 Series Reference Manual

RM0444

Figure 230. Control circuit in normal mode, internal clock divided by 1

r clock = CK_CNT = CK_PSC
24.3.4

Capture/compare channels

Each Capture/Compare channel is built around a capture/compare register (including a
shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and
an output stage (with comparator and output control).
Figure 231
The input stage samples the corresponding TIx input to generate a filtered signal TIxF.
Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be
used as the capture command. It is prescaled before the capture register (ICxPS).

Figure 231. Capture/compare channel (example: channel 1 input stage)

TIMx_CH1
The output stage generates an intermediate waveform which is then used for reference:
OCxRef (active high). The polarity acts at the end of the chain.
Internal clock
CEN=CNT_EN
UG
CNT_INIT
Counter register
31
to Figure 233 give an overview of one capture/compare channel.
TI1[0]
TI1[1..15]
Filter
downcounter
TI1F Edge
f
DTS
ICF[3:0]
TIMx_CCMR1
3 2 33 34 35 36
TI1F_Rising
0
TI1F_Falling
detector
1
CC1P/CC1NP
TIMx_CCER
RM0444 Rev 5
General-purpose timers (TIM14)
00 01 02 03 04 05
TI1FP1
01
IC1
/1, /2, /4, /8
CC1S[1:0] ICPS[1:0]
TIMx_CCMR1
06 07
MS31085V2
IC1PS
Divider
CC1E
TIMx_CCER
MSv45749V1
723/1390
740