Dac Sample And Hold Time Register (Dac_Shhr); Dac Sample And Hold Refresh Time Register (Dac_Shrr) - ST STM32G0 1 Series Reference Manual

Digital-to-analog converter (DAC)
16.7.19

DAC sample and hold time register (DAC_SHHR)

Address offset: 0x48
Reset value: 0x0001 0001
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:26 Reserved, must be kept at reset value.
Bits 25:16 THOLD2[9:0]: DAC channel2 hold time (only valid in Sample and hold mode).
Hold time= (THOLD[9:0]) x LSI clock period
Note: This register can be modified only when EN2=0.
Bits 15:10 Reserved, must be kept at reset value.
Bits 9:0 THOLD1[9:0]: DAC channel1 hold time (only valid in Sample and hold mode)
Hold time= (THOLD[9:0]) x LSI clock period
Note: This register can be modified only when EN1=0.
Note: These bits can be written only when the DAC channel is disabled and in Normal operating
mode (when bit ENx=0 and bit CENx=0 in the DAC_CR register). If ENx=1 or CENx=1 the
write operation is ignored.
16.7.20

DAC sample and hold refresh time register (DAC_SHRR)

Address offset: 0x4C
Reset value: 0x0001 0001
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
438/1390
28 27 26 25
Res. Res.
rw
12 11 10 9
Res. Res.
rw
These bits are available only on dual-channel DACs. Refer to
implementation.
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
24 23 22
rw rw rw
8 7 6
rw rw rw
24 23 22
Res.
rw rw
8 7 6
Res.
rw rw
RM0444 Rev 5
21 20 19 18
THOLD2[9:0]
rw rw rw rw
5 4 3 2
THOLD1[9:0]
rw rw rw rw
Section 16.3: DAC
21 20 19 18
TREFRESH2[7:0]
rw rw rw rw
5 4 3 2
TREFRESH1[7:0]
rw rw rw rw
RM0444
17 16
rw rw
1 0
rw rw
17 16
rw rw
1 0
rw rw