Usart Fifos And Thresholds; Usart Transmitter - ST STM32G0 1 Series Reference Manual

Universal synchonous receiver transmitter (USART)
33.5.4

USART FIFOs and thresholds

The USART can operate in FIFO mode.
The USART comes with a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). The
FIFO mode is enabled by setting FIFOEN in USART_CR1 register (bit 29). This mode is
supported only in UART, SPI and Smartcard modes.
Since the maximum data word length is 9 bits, the TXFIFO is 9-bit wide. However the
RXFIFO default width is 12 bits. This is due to the fact that the receiver does not only store
the data in the FIFO, but also the error flags associated to each character (Parity error,
Noise error and Framing error flags).
Note: The received data is stored in the RXFIFO together with the corresponding flags. However,
only the data are read when reading the RDR.
The status flags are available in the USART_ISR register.
It is possible to configure the TXFIFO and RXFIFO levels at which the Tx and RX interrupts
are triggered. These thresholds are programmed through RXFTCFG and TXFTCFG
bitfields in USART_CR3 control register.
In this case:
•
The RXFT flag is set in the USART_ISR register and the corresponding interrupt (if
enabled) is generated, when the number of received data in the RXFIFO reaches the
threshold programmed in the RXFTCFG bits fields.
This means that the RXFIFO is filled until the number of data in the RXFIFO is equal to
the programmed threshold.
RXFTCFG data have been received: one data in USART_RDR and (RXFTCFG - 1)
data in the RXFIFO. As an example, when the RXFTCFG is programmed to '101', the
RXFT flag is set when a number of data corresponding to the FIFO size has been
received (FIFO size -1 data in the RXFIFO and 1 data in the USART_RDR). As a
result, the next received data is not set the overrun flag.
• The TXFT flag is set in the USART_ISR register and the corresponding interrupt (if
enabled) is generated when the number of empty locations in the TXFIFO reaches the
threshold programmed in the TXFTCFG bits fields.
This means that the TXFIFO is emptied until the number of empty locations in the
TXFIFO is equal to the programmed threshold.
33.5.5

USART transmitter

The transmitter can send data words of either 7 or 8 or 9 bits, depending on the M bit status.
The Transmit Enable bit (TE) must be set in order to activate the transmitter function. The
data in the transmit shift register is output on the TX pin while the corresponding clock
pulses are output on the SCLK pin.
Character transmission
During an USART transmission, data shifts out the least significant bit first (default
configuration) on the TX pin. In this mode, the USART_TDR register consists of a buffer
(TDR) between the internal bus and the transmit shift register.
When FIFO mode is enabled, the data written to the transmit data register (USART_TDR)
are queued in the TXFIFO.
1006/1390 RM0444 Rev 5
RM0444