Tolerance Of The Lpuart Receiver To Clock Deviation; Table 191. Error Calculation For Programmed Baud Rates At Fck = 100 Mhz - ST STM32G0 1 Series Reference Manual

Low-power universal asynchronous receiver transmitter (LPUART)
Table 191. Error calculation for programmed baud rates at f
Baud rate
S.No Desired
1 38400 Baud
2 57600 Baud
3 115200 Baud
4 230400 Baud
5 460800 Baud
6 921600 Baud
7 4000 KBaud
8 10000 Kbaud
9 20000 Kbaud
10 30000 Kbaud
34.4.8

Tolerance of the LPUART receiver to clock deviation

The asynchronous receiver of the LPUART works correctly only if the total clock system
deviation is less than the tolerance of the LPUART receiver. The causes which contribute to
the total deviation are:
•
DTRA: deviation due to the transmitter error (which also includes the deviation of the
transmitter's local oscillator)
•
DQUANT: error due to the baud rate quantization of the receiver
•
DREC: deviation of the receiver local oscillator
•
DTCL: deviation due to the transmission line (generally due to the transceivers which
can introduce an asymmetry between the low-to-high transition timing and the high-to-
low transition timing)
where
The LPUART receiver can receive data correctly at up to the maximum tolerated deviation
specified in
• Number of Stop bits defined through STOP[1:0] bits in the LPUART_CR2 register
•
LPUART_BRR register value.
1100/1390
Value programmed in the baud
Actual
38400,04 Baud
57600,06 Baud
115200,12 Baud
230400,23 Baud
460804,61 Baud
921625,81 Baud
4000000,00 Baud
10000000,00 Baud
20000000,00 Baud
33032258,06 Baud
DTRA DQUANT
+ +
DWU is the error due to sampling point deviation when the wakeup from low-
power mode is used.
Table 192:
= 100MHz
f
CK
rate register
A2C2A
6C81C
3640E
1B207
D903
6C81
1900
A00
500
307
DREC DTCL DWU
+ +
RM0444 Rev 5
= 100 MHz
CK
% Error = (Calculated - Desired)
B.rate / Desired B.rate
0,0001
0,0001
0,0001
0,0001
0,001
0,0028
< LPUART receiver tolerance
RM0444
0
0
0
0,1