Dma Requests - ST STM32G0 1 Series Reference Manual

Inter-integrated circuit (I2C) interface
When a timeout violation is detected in master mode, a STOP condition is automatically
sent.
When a timeout violation is detected in slave mode, SDA and SCL lines are automatically
released.
When a timeout error is detected, the TIMEOUT flag is set in the I2C_ISR register, and an
interrupt is generated if the ERRIE bit is set in the I2C_CR1 register.
Alert (ALERT)
This section is relevant only when the SMBus feature is supported. Refer to
I2C implementation.
The ALERT flag is set when the I2C interface is configured as a Host (SMBHEN=1), the
alert pin detection is enabled (ALERTEN=1) and a falling edge is detected on the SMBA pin.
An interrupt is generated if the ERRIE bit is set in the I2C_CR1 register.
32.4.18

DMA requests

Transmission using DMA
DMA (Direct Memory Access) can be enabled for transmission by setting the TXDMAEN bit
in the I2C_CR1 register. Data is loaded from an SRAM area configured using the DMA
peripheral (see
register whenever the TXIS bit is set.
Only the data are transferred with DMA.
•
In master mode: the initialization, the slave address, direction, number of bytes and
START bit are programmed by software (the transmitted slave address cannot be
transferred with DMA). When all data are transferred using DMA, the DMA must be
initialized before setting the START bit. The end of transfer is managed with the
NBYTES counter. Refer to
•
In slave mode:
–
–
•
For instances supporting SMBus: the PEC transfer is managed with NBYTES counter.
Refer to
page
Note: If DMA is used for transmission, the TXIE bit does not need to be enabled.
Reception using DMA
DMA (Direct Memory Access) can be enabled for reception by setting the RXDMAEN bit in
the I2C_CR1 register. Data is loaded from the I2C_RXDR register to an SRAM area
configured using the DMA peripheral (refer to
(DMA) on page
transferred with DMA.
• In master mode, the initialization, the slave address, direction, number of bytes and
START bit are programmed by software. When all data are transferred using DMA, the
978/1390
Section 10: Direct memory access controller
With NOSTRETCH=0, when all data are transferred using DMA, the DMA must be
initialized before the address match event, or in ADDR interrupt subroutine, before
clearing ADDR.
With NOSTRETCH=1, the DMA must be initialized before the address match
event.
SMBus Slave transmitter on page 968
972.
277) whenever the RXNE bit is set. Only the data (including PEC) are
Master transmitter on page
and
Section 10: Direct memory access controller
RM0444 Rev 5
Section 32.3:
(DMA)) to the I2C_TXDR
953.
SMBus Master transmitter on
RM0444