Clock Selection; Figure 124. Control Circuit In Normal Mode, Internal Clock Divided By 1 - ST STM32G0 1 Series Reference Manual

Advanced-control timer (TIM1)
21.3.5

Clock selection

The counter clock can be provided by the following clock sources:
•
Internal clock (CK_INT)
•
External clock mode1: external input pin
•
External clock mode2: external trigger input ETR
•
Encoder mode
Internal clock source (CK_INT)
If the slave mode controller is disabled (SMS=000), then the CEN, DIR (in the TIMx_CR1
register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed
only by software (except UG which remains cleared automatically). As soon as the CEN bit
is written to 1, the prescaler is clocked by the internal clock CK_INT.
Figure 124
without prescaler.

Figure 124. Control circuit in normal mode, internal clock divided by 1

CEN=CNT_EN
Counter clock = CK_CNT = CK_PSC
Counter register
External clock source mode 1
This mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count at
each rising or falling edge on a selected input.
542/1390
shows the behavior of the control circuit and the upcounter in normal mode,
Internal clock
UG
CNT_INIT
31 3 2 33 34 35 36
RM0444 Rev 5
00 01 02 03 04 05
RM0444
06 07
MS31085V2