Wwdg Block Diagram; Enabling The Watchdog; Controlling The Down-Counter; How To Program The Watchdog Timeout - ST STM32G0 1 Series Reference Manual

System window watchdog (WWDG)
29.3.1

WWDG block diagram

pclk
29.3.2

Enabling the watchdog

When the user option WWDG_SW selects "Software window watchdog", the watchdog is
always disabled after a reset. It is enabled by setting the WDGA bit in the WWDG_CR
register, then it cannot be disabled again except by a reset.
When the user option WWDG_SW selects "Hardware window watchdog", the watchdog is
always enabled after a reset, it cannot be disabled.
29.3.3

Controlling the down-counter

This down-counter is free-running, counting down even if the watchdog is disabled. When
the watchdog is enabled, the T6 bit must be set to prevent generating an immediate reset.
The T[5:0] bits contain the number of increments that represent the time delay before the
watchdog produces a reset. The timing varies between a minimum and a maximum value
due to the unknown status of the prescaler when writing to the WWDG_CR register (see
Figure 280). The
window: to prevent a reset, the down-counter must be reloaded when its value is lower than
the window register value and greater than 0x3F.
watchdog process.
Note: The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is
cleared).
29.3.4

How to program the watchdog timeout

Use the formula in
868/1390

Figure 279. Watchdog block diagram

Register interface
W[6:0]
WWDG_CFR
WWDG_SR
readback
WWDG_CR
T[6:0]
preload
7-bit DownCounter (CNT)
WDGTB
÷ 4096 ÷ 2
WWDG configuration register (WWDG_CFR)
Figure 280 to calculate the WWDG timeout.
RM0444 Rev 5
CMP = 1 when
T[6:0] > W[6:0]
Write to WWDG_CR
T[6:0]
cnt_out
Figure 280
WWDG
wwdg_out_rst
WDGA
T6
EWI wwdg_it
EWIF
contains the high limit of the
describes the window
RM0444
MS47214V1