Capture/Compare Channels; Figure 129. Capture/Compare Channel (Example: Channel 1 Input Stage); Figure 130. Capture/Compare Channel 1 Main Circuit - ST STM32G0 1 Series Reference Manual

Advanced-control timer (TIM1)
21.3.6

Capture/compare channels

Each Capture/Compare channel is built around a capture/compare register (including a
shadow register), an input stage for capture (with digital filter, multiplexing, and prescaler,
except for channels 5 and 6) and an output stage (with comparator and output control).
Figure 129
The input stage samples the corresponding TIx input to generate a filtered signal TIxF.
Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be
used as trigger input by the slave mode controller or as the capture command. It is
prescaled before the capture register (ICxPS).

Figure 129. Capture/compare channel (example: channel 1 input stage)

TIMx_TISEL[3:0]
TI1[0]
TIMx_CH1
TI1[1..15]
f
DTS
The output stage generates an intermediate waveform which is then used for reference:
OCxRef (active high). The polarity acts at the end of the chain.
Input mode
CC1S[1]
CC1S[0]
IC1PS
CC1E
CC1G
TIMx_EGR
546/1390
to Figure 132 give an overview of one Capture/Compare channel.
Filter
downcounter
TI1F
Edge
detector
ICF[3:0]
TIMx_CCMR1

Figure 130. Capture/compare channel 1 main circuit

APB Bus
MCU-peripheral interface
Capture/compare preload register
Capture
compare shadow register
Counter
RM0444 Rev 5
TI1F_ED
TI1F_Rising
0
TI1FP1
TI1F_Falling
1
TI2FP1
CC1P/CC1NP
TRC
TIMx_CCER
(from slave mode
controller)
TI2F_Rising
0
(from channel 2)
TI2F_Falling
1
(from channel 2)
16/32-bit
Compare
transfer
Comparator
To the slave mode controller
01
IC1
Divider
10
/1, /2, /4, /8
11
CC1S[1:0] ICPS[1:0]
TIMx_CCER
TIMx_CCMR1
Output mode
CC1S[1]
CC1S[0]
OC1PE
UEV
(from time
base unit)
CNT>CCR1
CNT=CCR1
RM0444
IC1PS
CC1E
MSv40120V2
OC1PE
TIMx_CCMR1
MSv63030V1