Low-Power Sleep Mode (Lp Sleep) - ST STM32G0 1 Series Reference Manual

Power control (PWR)
Characteristic
Mode exit
Wakeup latency
4.3.5

Low-power sleep mode (LP sleep)

Refer to the product datasheet for more details on voltage regulator and peripherals
operating conditions.
I/O states in Low-power sleep mode
In Low-power sleep mode, all I/O pins keep the same state as in Run mode.
Entering Low-power sleep mode
The MCU enters Low-power sleep mode from Low-power run mode according to
low-power
clear.
Refer to
sleep mode.
Exiting Low-power sleep mode
The MCU exits Low-power sleep mode according to
Low-power sleep mode by issuing an interrupt or an event, the MCU is in Low-power run
mode.
Refer to
sleep mode.
134/1390
Table 28. Sleep mode summary (continued)
If WFI or return from ISR was used for entry
Interrupt: refer to
If WFE was used for entry and SEVONPEND = 0:
Wakeup event: refer to
If WFE was used for entry and SEVONPEND = 1:
Interrupt even when disabled in NVIC: refer to
Wakeup event: refer to
None
modes, when the SLEEPDEEP bit in the Cortex
Table 29: Low-power sleep mode summary
Table 29: Low-power sleep mode summary
Description
Table 58: Vector table
Section 13.3.2: EXTI direct event input wakeup
Section 13.3.2: EXTI direct event input wakeup
for details on how to enter Low-power
Exiting low-power
for details on how to exit Low-power
RM0444 Rev 5
Table 58: Vector table
®
-M0+ System Control register is
modes. When exiting
RM0444
or
Entering