Rng Registers; Rng Control Register (Rng_Cr) - ST STM32G0 1 Series Reference Manual

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RNG registers

The RNG is associated with a control register, a data register and a status register.

Address offset: 0x000

Reset value: 0x0000 0000

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 CED: Clock error detection

Bit 4 Reserved, must be kept at reset value.

Bit 3 IE: Interrupt Enable

Bit 2 RNGEN: True random number generator enable

Bits 1:0 Reserved, must be kept at reset value.

0: Clock error detection is enable

1: Clock error detection is disable

The clock error detection cannot be enabled nor disabled on-the-fly when the RNG is

enabled, i.e. to enable or disable CED the RNG must be disabled.

0: RNG Interrupt is disabled

1: RNG Interrupt is enabled. An interrupt is pending as soon as DRDY='1', SEIS='1' or

CEIS=1 in the RNG_SR register.

0: True random number generator is disabled. Analog noise sources are powered off and

logic clocked by the RNG clock is gated.

1: True random number generator is enabled.

True random number generator (RNG)

RM0444 Rev 5

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