Adc Interrupts; Table 77. Adc Interrupts; Figure 58. Vbat Channel Block Diagram - ST STM32G0 1 Series Reference Manual

RM0444
the correct operation of the ADC, the V
This bridge is automatically enabled when VBATEN is set, to connect V
V [14] input channel. As a consequence, the converted digital value is half the V
IN
voltage. To prevent any unwanted consumption on the battery, it is recommended to enable
the bridge divider only when needed for ADC conversion.
15.11

ADC interrupts

An interrupt can be generated by any of the following events:
•
End Of Calibration (EOCAL flag)
•
ADC power-up, when the ADC is ready (ADRDY flag)
• End of any conversion (EOC flag)
•
End of a sequence of conversions (EOS flag)
• When an analog watchdog detection occurs (AWD1, AWD2, AWD3 flags)
•
When the Channel configuration is ready (CCRDY flag)
• When the end of sampling phase occurs (EOSMP flag)
•
when a data overrun occurs (OVR flag)
Separate interrupt enable bits are available for flexibility.
End Of Calibration
ADC ready
End of conversion
End of sequence of conversions
Analog watchdog 1 status bit is set
Figure 58. V
V
VBATEN control bit
BAT
V /3
BAT
+
-

Table 77. ADC interrupts

Interrupt event
pin is internally connected to a bridge divider.
BAT
channel block diagram
BAT
ADC V
RM0444 Rev 5
Analog-to-digital converter (ADC)
to the ADC
BAT
ADC
[14]
IN
Event flag Enable control bit
EOCAL
ADRDY ADRDYIE
EOC
EOS
AWD1
BAT
MSv45367V2
EOCALIE
EOCIE
EOSIE
AWD1IE
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