Table 59. Exti Signal Overview; Table 60. Evg Pin Overview; Figure 26. Exti Block Diagram - ST STM32G0 1 Series Reference Manual

Extended interrupt and event controller (EXTI)
AHB interface
hclk
IOPort
Configurable event(15:0)
Direct event(x) or
configurable event(y)
Wakeup
Interrupt
Direct event(x)
EXTI
* it_exti_per(y) are only available for configurable events (y)
Signal name
AHB interface
hclk
Configurable
event(y)
Direct event(x)
IOPort(n)
exti[15:0]
it_exti_per (y)
c_evt_exti
c_evt_rst
sys_wakeup
c_wakeup
Pin name
c_fclk
c_evt_in
c_event
c_evt_rst
318/1390

Figure 26. EXTI block diagram

Registers
Event
Trigger
Masking
events

Table 59. EXTI signal overview

I/O
EXTI register bus interface. When one event is configured to allow
I/O
security, the AHB interface support secure accesses
I AHB bus clock and EXTI system clock
Asynchronous wakeup events from peripherals that do not have an
I
associated interrupt and flag in the peripheral
Synchronous and asynchronous wakeup events from peripherals having
I
an associated interrupt and flag in the peripheral
I GPIO ports[15:0]
O EXTI output port to trigger other IPs
O Interrupts to the CPU associated with configurable event (y)
O High-level sensitive event output for CPU synchronous to hclk
I Asynchronous reset input to clear c_evt_exti
O Asynchronous system wakeup request to PWR for ck_sys and hclk
O Wakeup request to PWR for CPU, synchronous to hclk

Table 60. EVG pin overview

I/O
I CPU free-running clock
I High-level sensitive event input from EXTI, asynchronous to CPU clock
O Event pulse, synchronous to CPU clock
O Event reset signal, synchronous to CPU clock
RM0444 Rev 5
exti[15:0]
To interconnect
sys_wakeup
c_wakeup
it_exti_per(y)*
c_evt_exti c_event
Pulse
c_evt_rst
c_fclk
EVG
Description
Description
RM0444
PWR
rxev
CPU
MS44733V2