Cec Interrupt Enable Register (Cec_Ier) - ST STM32G0 1 Series Reference Manual

HDMI-CEC controller (CEC)
Bit 4 SBPE: Rx-short bit period error
SBPE is set by hardware in case a data-bit waveform is detected with short bit period error. SBPE is
set at the time the anticipated falling edge occurs. SBPE generates an error-bit on the CEC line.
SBPE is cleared by software write at 1.
Bit 3 BRE: Rx-bit rising error
BRE is set by hardware in case a data-bit waveform is detected with bit rising error. BRE is set either
at the time the misplaced rising edge occurs, or at the end of the maximum BRE tolerance allowed
by RXTOL, in case rising edge is still longing. BRE stops message reception if BRESTP = 1. BRE
generates an error-bit on the CEC line if BREGEN = 1.
BRE is cleared by software write at 1.
Bit 2 RXOVR: Rx-overrun
RXOVR is set by hardware if RXBR is not yet cleared at the time a new byte is received on the CEC
line and stored into RXD. RXOVR assertion stops message reception so that no acknowledge is
sent. In case of broadcast, a negative acknowledge is sent.
RXOVR is cleared by software write at 1.
Bit 1 RXEND: End of reception
RXEND is set by hardware to inform application that the last byte of a CEC message is received
from the CEC line and stored into the RXD buffer. RXEND is set at the same time of RXBR.
RXEND is cleared by software write at 1.
Bit 0 RXBR: Rx-byte received
The RXBR bit is set by hardware to inform application that a new byte has been received from the
CEC line and stored into the RXD buffer.
RXBR is cleared by software write at 1.
39.7.6

CEC interrupt enable register (CEC_IER)

Address offset: 0x14
Reset value: 0x0000 0000
Caution: It is mandatory to write CEC_IER only when CECEN = 0.
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
TXACK
Res. Res. Res.
IE
rw
Bits 31:13 Reserved, must be kept at reset value.
Bit 12 TXACKIE: Tx-missing acknowledge error interrupt enable
The TXACKEIE bit is set and cleared by software.
0: TXACKE interrupt disabled
1: TXACKE interrupt enabled
Bit 11 TXERRIE: Tx-error interrupt enable
The TXERRIE bit is set and cleared by software.
0: TXERR interrupt disabled
1: TXERR interrupt enabled
1362/1390
27 26 25 24
Res. Res. Res. Res.
11 10 9
TXERR TX TXEND TXBR
IE UDRIE IE IE
rw rw rw rw
RM0444 Rev 5
23 22 21
Res. Res. Res.
8 7 6 5
ARBLST RXACK LBPE
IE IE IE
rw rw rw
20 19 18 17
Res. Res. Res. Res.
4 3 2 1
SBPE RXOVR RXEND
BREIE
IE IE IE
rw rw rw rw
RM0444
16
Res.
0
RXBR
IE
rw