Flash Memory Acceleration - ST STM32G0 1 Series Reference Manual

RM0444
Decreasing the CPU frequency
1. Modify the system clock source by writing the SW bits of the RCC_CFGR register.
2. If needed, modify the core clock prescaler by writing the HPRE bits of RCC_CFGR.
3. Check that the new system clock source or/and the new core clock prescaler value
is/are taken into account by reading the clock source status (SWS bits) of the
RCC_CFGR register, or/and the AHB prescaler value (HPREF bit), of the RCC_CFGR
register, and wait until the programmed new system clock source or/and new Flash
memory clock prescaler value is/are read.
4. Program the new number of wait states to the LATENCY bits of the
control register
5. Optionally, check that the new number of wait states is used to access the Flash
memory by reading back the LATENCY bits of the
(FLASH_ACR).
3.3.5

FLASH memory acceleration

Instruction prefetch
Each Flash memory read operation provides 64 bits from either two instructions of 32 bits or
four instructions of 16 bits according to the program launched. This 64-bits current
instruction line is saved in a current buffer. So, in case of sequential code, at least two CPU
cycles are needed to execute the previous read instruction line. Prefetch on the CPU S-bus
can be used to read the next sequential instruction line from the Flash memory while the
current instruction line is being requested by the CPU.
Prefetch is enabled by setting the PRFTEN bit of the
(FLASH_ACR). This feature is useful if at least one wait state is needed to access the Flash
memory.
When the code is not sequential (branch), the instruction may not be present in the currently
used instruction line or in the prefetched instruction line. In this case (miss), the penalty in
terms of number of cycles is at least equal to the number of wait states.
If a loop is present in the current buffer, no new access is performed.
Cache memory
To limit the time lost due to jumps, it is possible to retain two cache lines of 64 bits (16 bytes)
in the instruction cache memory. This feature can be enabled by setting the instruction
cache enable (ICEN) bit of the
miss occurs (requested data not present in the currently used instruction line, in the
prefetched instruction line or in the instruction cache memory), the line read is copied into
the instruction cache memory. If some data contained in the instruction cache memory are
requested by the CPU, they are provided without inserting any delay. Once all the
instruction cache memory lines are filled, the LRU (least recently used) policy is used to
determine the line to replace in the instruction memory cache. This feature is particularly
useful in case of code containing loops.
The Instruction cache memory is enabled after system reset.
No data cache is available on Cortex
(FLASH_ACR).
FLASH access control register
®
-M0+.
RM0444 Rev 5
Embedded Flash memory (FLASH)
FLASH access
FLASH access control register
FLASH access control register
(FLASH_ACR). Each time a
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