Fdcan Registers; Fdcan Core Release Register (Fdcan_Crel); Fdcan Endian Register (Fdcan_Endn) - ST STM32G0 1 Series Reference Manual

RM0444
36.4

FDCAN registers

36.4.1

FDCAN core release register (FDCAN_CREL)

Address offset: 0x0000
Reset value: 0x3214 1218
31 30 29
REL[3:0]
r r r
15 14 13
r r r
Bits 31:28 REL[3:0]: 3
Bits 27:24 STEP[3:0]: 2
Bits 23:20 SUBSTEP[3:0]: 1
Bits 19:16 YEAR[3:0]: 4
Bits 15:8 MON[7:0]: 12
Bits 7:0 DAY[7:0]: 18
36.4.2

FDCAN endian register (FDCAN_ENDN)

Address offset: 0x0004
Reset value: 0x8765 4321
31 30 29
r r r
15 14 13
r r r
Bits 31:0 ETV[31:0]: Endianness test value
The endianness test value is 0x8765 4321.
Note: The register read must give the reset value to ensure no endiandess issue.
28 27 26 25
STEP[3:0]
r r r r
12 11 10 9
MON[7:0]
r r r r
28 27 26 25
r r r r
12 11 10 9
r r r r
FD controller area network (FDCAN)
24 23 22
SUBSTEP[3:0]
r r r
8 7 6
r r r
24 23 22
ETV[31:16]
r r r
8 7 6
ETV[15:0]
r r r
RM0444 Rev 5
21 20 19 18
YEAR[3:0]
r r r r
5 4 3 2
DAY[7:0]
r r r r
21 20 19 18
r r r r
5 4 3 2
r r r r
17 16
r r
1 0
r r
17 16
r r
1 0
r r
1227/1390
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