Low-Power Modes - ST STM32G0 1 Series Reference Manual

RM0444
5.3

Low-power modes

• AHB and APB peripheral clocks, including DMA clock, can be disabled by software.
•
Sleep and Low Power Sleep modes stops the CPU clock. The memory interface clocks
(Flash memory and SRAM interfaces) can be stopped by software during sleep mode.
The AHB to APB bridge clocks are disabled by hardware during Sleep mode when all
the clocks of the peripherals connected to them are disabled.
•
Stop modes (Stop 0 and Stop 1) stop all the clocks in the V
the PLL as well as the HSI16, HSI48 and HSE oscillators.
The USART1, USART2, USART3, LPUART1, LPUART2, I2C1, and I2C2 peripherals
can enable the HSI16 oscillator even when the MCU is in Stop mode (if HSI16 is
selected as clock source for one of those peripherals).
The LPUART1, LPUART2, USART1, USART2, and USART3 peripherals can also
operate with the clock from the LSE oscillator when the system is in Stop mode, if LSE
is selected as clock source for that peripheral and the LSE oscillator is enabled
(LSEON set). In that case, the LSE oscillator remains active when the device enters
Stop mode (these peripherals do not have the capability to turn on the LSE oscillator).
•
Standby and Shutdown modes stop all clocks in the V
PLL, as well as the HSI16, HSI48, and HSE oscillators.
The CPU deepsleep mode can be overridden for debugging, by setting the DBG_STOP or
DBG_STANDBY bits in the DBGMCU_CR register.
When leaving the Stop 0 or Stop 1 modes, HSISYS becomes automatically the system
clock.
When leaving the Standby and Shutdown modes, HSISYS (with frequency equal to HSI16)
becomes automatically the system clock. At wakeup from Standby and Shutdown mode, the
user trim is lost.
If a Flash memory programming operation is ongoing, Stop, Standby, and Shutdown entry is
delayed until the Flash memory interface access is finished. If an access to the APB domain
is ongoing, the Stop, Standby, and Shutdown entry is delayed until the APB access is
finished.
RM0444 Rev 5
Reset and clock control (RCC)
domain and disable
CORE
domain and disable the
CORE
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