Dp And Ap Read/Write Accesses; Sw-Dp Registers; Table 251. Sw-Dp Registers - ST STM32G0 1 Series Reference Manual

RM0444
Note: Note that the SW-DP state machine is inactive until the target reads this ID code.
•
The SW-DP state machine is in RESET STATE either after power-on reset, or after the
line is high for more than 50 cycles
•
The SW-DP state machine is in IDLE STATE if the line is low for at least two cycles
after RESET state.
•
After RESET state, it is mandatory to first enter into an IDLE state AND to perform a
READ access of the DP-SW ID CODE register. Otherwise, the target issues a FAULT
acknowledge response on another transactions.
Further details of the SW-DP state machine can be found in the Cortex
CoreSight Design Kit r1p0 TRM.
40.5.4

DP and AP read/write accesses

•
Read accesses to the DP are not posted: the target response can be immediate (if
ACK=OK) or can be delayed (if ACK=WAIT).
•
Read accesses to the AP are posted. This means that the result of the access is
returned on the next transfer. If the next access to be done is NOT an AP access, then
the DP-RDBUFF register must be read to obtain the result.
The READOK flag of the DP-CTRL/STAT register is updated on every AP read access
or RDBUFF read request to know if the AP read access was successful.
•
The SW-DP implements a write buffer (for both DP or AP writes), that enables it to
accept a write operation even when other transactions are still outstanding. If the write
buffer is full, the target acknowledge response is "WAIT". With the exception of
IDCODE read or CTRL/STAT read or ABORT write which are accepted even if the write
buffer is full.
•
Because of the asynchronous clock domains SWCLK and HCLK, two extra SWCLK
cycles are needed after a write transaction (after the parity bit) to make the write
effective internally. These cycles should be applied while driving the line low (IDLE
state)
This is particularly important when writing the CTRL/STAT for a power-up request. If the
next transaction (requiring a power-up) occurs immediately, it fails.
40.5.5

SW-DP registers

Access to these registers are initiated when APnDP=0
A[3:2] R/W
00 Read
00 Write

Table 251. SW-DP registers

CTRLSEL bit
of SELECT Register
register
IDCODE
ABORT
RM0444 Rev 5
Notes
The manufacturer code is set to the default
®
Arm code for Cortex -M0+:
0x0BC11477 (identifies the SW-DP)
Debug support (DBG)
®
-M0+ TRM and the
1369/1390
1378