I/O Port In Sleep Mode Clock Enable Register (Rcc_Iopsmenr) - ST STM32G0 1 Series Reference Manual

Reset and clock control (RCC)
Bit 18 TIM17EN: TIM16 timer clock enable
Bit 17 TIM16EN: TIM16 timer clock enable
Bit 16 TIM15EN: TIM15 timer clock enable
Bit 15 TIM14EN: TIM14 timer clock enable
Bit 14 USART1EN: USART1 clock enable
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1EN: SPI1 clock enable
Bit 11 TIM1EN: TIM1 timer clock enable
Bits 10:1 Reserved, must be kept at reset value.
Bit 0 SYSCFGEN: SYSCFG, COMP and VREFBUF clock enable
5.4.17

I/O port in Sleep mode clock enable register (RCC_IOPSMENR)

Address: 0x44
Reset value: 0x0000 003F
31 30 29
Res. Res. Res. Res.
202/1390
Set and cleared by software.
0: Disable
1: Enable
Set and cleared by software.
0: Disable
1: Enable
Set and cleared by software.
0: Disable
1: Enable
Set and cleared by software.
0: Disable
1: Enable
Set and cleared by software.
0: Disable
1: Enable
Set and cleared by software.
0: Disable
1: Enable
Set and cleared by software.
0: Disable
1: Enable
Set and cleared by software.
0: Disable
1: Enable
28 27 26 25
Res. Res. Res.
(1)
24 23 22
Res. Res. Res. Res.
RM0444 Rev 5
21 20 19 18
Res. Res. Res.
RM0444
17 16
Res. Res.