Fdcan Cc Control Register (Fdcan_Cccr) - ST STM32G0 1 Series Reference Manual

FD controller area network (FDCAN)
RAM until the counter has counted down to 0, the counter stops and interrupt flag IR[WDI]
bit is set. The RAM Watchdog Counter is clocked by the fdcan_pclk clock.
Address offset: 0x0014
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
r r r
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:8 WDV[7:0]: Watchdog value
Actual message RAM watchdog counter value.
Bits 7:0 WDC[7:0]: Watchdog configuration
Start value of the message RAM watchdog counter. With the reset value of 00, the counter is
disabled.
These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit
0 [INIT] of FDCAN_CCCR register are set to 1.
36.4.6

FDCAN CC control register (FDCAN_CCCR)

Address offset: 0x0018
Reset value: 0x0000 0001
For details about setting and resetting of single bits, see
31 30 29
Res. Res. Res. Res.
15 14 13
NISO TXP EFBI PXHD
rw rw rw
1230/1390
28 27 26 25
Res. Res. Res.
12 11 10 9
WDV[7:0]
r r r r
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. BRSE
rw rw
24 23 22
Res. Res. Res.
8 7 6
r rw rw
24 23 22
Res. Res. Res.
8 7 6
FDOE TEST DAR MON
rw rw rw
RM0444 Rev 5
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
WDC[7:0]
rw rw rw rw
Software initialization.
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
CSR CSA ASM
rw rw r rw
RM0444
17 16
Res. Res.
1 0
rw rw
17 16
Res. Res.
1 0
CCE INIT
rw rw