Tamp Masked Interrupt Status Register (Tamp_Misr) - ST STM32G0 1 Series Reference Manual

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Bits 31:24 Reserved, must be kept at reset value.

Bit 23 Reserved, must be kept at reset value.

Bit 22 Reserved, must be kept at reset value.

Bit 21 ITAMP6F: ST manufacturer readout tamper detection flag

Bit 20 ITAMP5F: RTC calendar overflow tamper detection flag

Bit 19 ITAMP4F: HSE monitoring tamper detection flag

Bit 18 ITAMP3F: LSE monitoring tamper detection flag

Bit 17 Reserved, must be kept at reset value.

Bit 16 Reserved, must be kept at reset value.

Bits 15:3 Reserved, must be kept at reset value.

Bit 2 TAMP3F: TAMP3 detection flag

Bit 1 TAMP2F: TAMP2 detection flag

Bit 0 TAMP1F: TAMP1 detection flag

TAMP masked interrupt status register (TAMP_MISR)

Address offset: 0x34

Backup domain reset value: 0x0000 0000

System reset: not affected

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 Reserved, must be kept at reset value.

Bit 22 Reserved, must be kept at reset value.

This flag is set by hardware when a tamper detection event is detected on the internal

This flag is set by hardware when a tamper detection event is detected on the internal

This flag is set by hardware when a tamper detection event is detected on the internal

This flag is set by hardware when a tamper detection event is detected on the internal

This flag is set by hardware when a tamper detection event is detected on the TAMP3 input.

This flag is set by hardware when a tamper detection event is detected on the TAMP2 input.

This flag is set by hardware when a tamper detection event is detected on the TAMP1 input.

Tamper and backup registers (TAMP)

RM0444 Rev 5

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