Fdcan Interrupt Line Enable Register (Fdcan_Ile); Fdcan Global Filter Configuration Register (Fdcan_Rxgfc) - ST STM32G0 1 Series Reference Manual

RM0444
Bit 1 RxFIFO1: RX FIFO bit grouping the following interruption
RF1LL: Rx FIFO 1 message lost interrupt line
RF1FL: Rx FIFO 1 full Interrupt line
RF1NL: Rx FIFO 1 new message interrupt line
Bit 0 RxFIFO0: RX FIFO bit grouping the following interruption
RF0LL: Rx FIFO 0 message lost interrupt line
RF0FL: Rx FIFO 0 full interrupt line
RF0NL: Rx FIFO 0 new message interrupt line
36.4.18

FDCAN interrupt line enable register (FDCAN_ILE)

Each of the two interrupt lines to the CPU can be enabled/disabled separately by
programming bits EINT0 and EINT1.
Address offset: 0x005C
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 EINT1: Enable interrupt line 1
0: Interrupt line fdcan_intr0_it disabled
1: Interrupt line fdcan_intr0_it enabled
Bit 0 EINT0: Enable interrupt line 0
0: Interrupt line fdcan_intr1_it disabled
1: Interrupt line fdcan_intr1_it enabled
36.4.19

FDCAN global filter configuration register (FDCAN_RXGFC)

Global settings for Message ID filtering. The Global Filter Configuration controls the filter
path for standard and extended messages as described in
Address offset: 0x0080
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
28 27 26 25
LSE[3:0]
rw rw rw
12 11 10 9
Res. Res. F0OM
rw
FD controller area network (FDCAN)
24 23 22
Res. Res. Res.
8 7 6
Res. Res. Res.
24 23 22
Res. Res.
rw
8 7 6
F1OM Res. Res.
rw
RM0444 Rev 5
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
Res. Res. Res. Res.
Figure 399 and Figure
21 20 19 18
Res. LSS[4:0]
rw rw rw
5 4 3 2
ANFS[1:0] ANFE[1:0]
rw rw rw rw
17 16
Res. Res.
1 0
EINT1 EINT0
rw rw
400.
17 16
rw rw
1 0
RRFS RRFE
rw rw
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