Embedded Sram; Table 7. Sram Size - ST STM32G0 1 Series Reference Manual

RM0444
Table 6. STM32G0x1 peripheral register boundary addresses (continued)
Bus Boundary address
0x4000 5800 - 0x4000 5BFF
0x4000 5400 - 0x4000 57FF
0x4000 5000 - 0x4000 53FF
0x4000 4C00 - 0x4000 4FFF
0x4000 4800 - 0x4000 4BFF
0x4000 4400 - 0x4000 47FF
0x4000 4000 - 0x4000 43FF
0x4000 3C00 - 0x4000 3FFF
0x4000 3800 - 0x4000 3BFF
0x4000 3400 - 0x4000 37FF
0x4000 3000 - 0x4000 33FF
APB
0x4000 2C00 - 0x4000 2FFF
0x4000 2800 - 0x4000 2BFF
0x4000 2400 - 0x4000 27FF
0x4000 2000 - 0x4000 23FF
0x4000 1800 - 0x4000 1FFF
0x4000 1400 - 0x4000 17FF
0x4000 1000 - 0x4000 13FF
0x4000 0C00 - 0x4000 0FFF
0x4000 0800 - 0x4000 0BFF
0x4000 0400 - 0x4000 07FF
0x4000 0000 - 0x4000 03FF
1. SYSCFG (ITLINE) registers use 0x4001 0000 as reference peripheral base address.
2.3

Embedded SRAM

The following table summarizes the SRAM resources on the devices, with parity check
enabled and disabled.
.
STM32G0B1xx and STM32G0C1xx
STM32G071xx and STM32G081xx
STM32G051xx and STM32G061xx
STM32G031xx and STM32G041xx
Size
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB
2 KB
1 KB
1 KB
1 KB
1 KB
1 KB
1 KB

Table 7. SRAM size

Device
RM0444 Rev 5
Peripheral
I2C2
I2C1
USART5
USART4
USART3
USART2
Reserved
SPI3
SPI2/I2S2
Reserved
IWDG
WWDG
RTC
Reserved
TIM14
Reserved
TIM7
TIM6
Reserved
TIM4
TIM3
TIM2
SRAM with parity enabled
(Kbyte)
128
32
16
8
Peripheral register map
Section 32.7.12 on page 998
Section 32.7.12 on page 998
Section 33.8.15 on page 1086
Section 33.8.15 on page 1086
Section 33.8.15 on page 1086
Section 33.8.15 on page 1086
-
Section 35.9.10 on page 1197
Section 35.9.10 on page 1197
-
Section 28.4.6 on page 868
Section 29.5.4 on page 874
Section 30.6.21 on page 912
-
Section 24.4.13 on page 740
-
Section 23.4.9 on page 715
Section 23.4.9 on page 715
-
Section 22.4.31 on page 700
Section 22.4.31 on page 700
Section 22.4.31 on page 700
SRAM with parity disabled
(Kbyte)
144
36
18
8
65/1391
68