Dac Channel1 Sample And Hold Sample Time Register; (Dac_Shsr1); Dac Channel2 Sample And Hold Sample Time Register; (Dac_Shsr2) - ST STM32G0 1 Series Reference Manual

RM0444
16.7.17

DAC channel1 sample and hold sample time register

(DAC_SHSR1)

Address offset: 0x40
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:10 Reserved, must be kept at reset value.
Bits 9:0 TSAMPLE1[9:0]: DAC channel1 sample time (only valid in Sample and hold mode)
These bits can be written when the DAC channel1 is disabled or also during normal operation.
in the latter case, the write can be done only when BWST1 of DAC_SR register is low, If
BWST1=1, the write operation is ignored.
Note: It represents the number of LSI clocks to perform a sample phase. Sampling time =
(TSAMPLE1[9:0] + 1) x LSI clock period.
16.7.18

DAC channel2 sample and hold sample time register

(DAC_SHSR2)

This register is available only on dual-channel DACs. Refer to
implementation.
Address offset: 0x44
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:10 Reserved, must be kept at reset value.
Bits 9:0 TSAMPLE2[9:0]: DAC channel2 sample time (only valid in Sample and hold mode)
These bits can be written when the DAC channel2 is disabled or also during normal
operation. in the latter case, the write can be done only when BWST2 of DAC_SR register is
low, if BWST2=1, the write operation is ignored.
Note: It represents the number of LSI clocks to perform a sample phase. Sampling time =
(TSAMPLE1[9:0] + 1) x LSI clock period.
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res.
rw
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res.
rw
24 23 22
Res. Res. Res.
8 7 6
TSAMPLE1[9:0]
rw rw rw
24 23 22
Res. Res. Res.
8 7 6
TSAMPLE2[9:0]
rw rw rw
RM0444 Rev 5
Digital-to-analog converter (DAC)
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
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Section 16.3: DAC
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
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17 16
Res. Res.
1 0
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17 16
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1 0
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