Lptim Autoreload Register (Lptim_Arr); Lptim Counter Register (Lptim_Cnt) - ST STM32G0 1 Series Reference Manual

RM0444
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 CMP[15:0]: Compare value
CMP is the compare value used by the LPTIM.
Caution: The LPTIM_CMP register must only be modified when the LPTIM is enabled (ENABLE bit
set to '1').
26.7.7

LPTIM autoreload register (LPTIM_ARR)

Address offset: 0x018
Reset value: 0x0000 0001
31 30 29
Res. Res. Res. Res.
15 14 13
rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 ARR[15:0]: Auto reload value
ARR is the autoreload value for the LPTIM.
This value must be strictly greater than the CMP[15:0] value.
Caution: The LPTIM_ARR register must only be modified when the LPTIM is enabled (ENABLE bit
set to '1').
26.7.8

LPTIM counter register (LPTIM_CNT)

Address offset: 0x01C
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
r r r
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 CNT[15:0]: Counter value
When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may
return unreliable values. So in this case it is necessary to perform two consecutive read accesses
and verify that the two returned values are identical.
It should be noted that for a reliable LPTIM_CNT register read access, two consecutive read
accesses must be performed and compared. A read access can be considered reliable when the
values of the two consecutive read accesses are equal.
28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw rw
28 27 26 25
Res. Res. Res.
12 11 10 9
r r r r
24 23 22
Res. Res. Res.
8 7 6
ARR[15:0]
rw rw rw
24 23 22
Res. Res. Res.
8 7 6
CNT[15:0]
r r r
RM0444 Rev 5
Low-power timer (LPTIM)
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
rw rw rw rw
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
r r r r
17 16
Res. Res.
1 0
rw rw
17 16
Res. Res.
1 0
r r
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