Tim16/Tim17 Registers; Timx Control Register 1 (Timx_Cr1)(X = 16 To 17) - ST STM32G0 1 Series Reference Manual

RM0444
25.6

TIM16/TIM17 registers

Refer to
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).
25.6.1

TIMx control register 1 (TIMx_CR1)(x = 16 to 17)

Address offset: 0x00
Reset value: 0x0000
15 14 13
Res. Res. Res. Res.
Bits 15:12 Reserved, must be kept at reset value.
Bit 11 UIFREMAP: UIF status bit remapping
Bit 10 Reserved, must be kept at reset value.
Bits 9:8 CKD[1:0]: Clock division
Bit 7 ARPE: Auto-reload preload enable
Bits 6:4 Reserved, must be kept at reset value.
Bit 3 OPM: One pulse mode
Bit 2 URS: Update request source
Section 1.2 for a list of abbreviations used in register descriptions.
12 11 10 9
UIFRE
Res. CKD[1:0]
MAP
rw rw
0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31.
1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31.
This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the
dead-time and sampling clock (t
(TIx),
00: t = t
DTS CK_INT
01: t = 2 * t
DTS CK_INT
10: t = 4 * t
DTS CK_INT
11: Reserved, do not program this value
0: TIMx_ARR register is not buffered
1: TIMx_ARR register is buffered
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the bit CEN)
This bit is set and cleared by software to select the UEV event sources.
0: Any of the following events generate an update interrupt or DMA request if enabled.
These events can be:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
1: Only counter overflow/underflow generates an update interrupt or DMA request if
enabled.
General-purpose timers (TIM15/TIM16/TIM17)
8 7 6
ARPE Res.
rw rw
)used by the dead-time generators and the digital filters
DTS
RM0444 Rev 5
5 4 3 2
Res. Res. OPM URS
rw rw
1 0
UDIS CEN
rw rw
807/1390
830