Dac Registers; Dac Control Register (Dac_Cr) - ST STM32G0 1 Series Reference Manual

Digital-to-analog converter (DAC)
16.7

DAC registers

Refer to
The peripheral registers have to be accessed by words (32-bit).
16.7.1

DAC control register (DAC_CR)

Address offset: 0x00
Reset value: 0x0000 0000
31 30 29 28
DMAU DMAE
Res. CEN2
DRIE2 N2
rw rw rw
15 14 13 12
DMAU DMAE
Res. CEN1
DRIE1 N1
rw rw rw
Bit 31 Reserved, must be kept at reset value.
Bit 30 CEN2: DAC channel2 calibration enable
This bit is set and cleared by software to enable/disable DAC channel2 calibration, it can be
written only if EN2 bit is set to 0 into DAC_CR (the calibration mode can be entered/exit only
when the DAC channel is disabled) Otherwise, the write operation is ignored.
0: DAC channel2 in Normal operating mode
1: DAC channel2 in calibration mode
Note: This bit is available only on dual-channel DACs. Refer to
Bit 29 DMAUDRIE2: DAC channel2 DMA underrun interrupt enable
This bit is set and cleared by software.
0: DAC channel2 DMA underrun interrupt disabled
1: DAC channel2 DMA underrun interrupt enabled
Note: This bit is available only on dual-channel DACs. Refer to
Bit 28 DMAEN2: DAC channel2 DMA enable
This bit is set and cleared by software.
0: DAC channel2 DMA mode disabled
1: DAC channel2 DMA mode enabled
Note: This bit is available only on dual-channel DACs. Refer to
424/1390
Section 1 on page 53
27 26 25
MAMP2[3:0]
rw rw rw
11 10 9
MAMP1[3:0]
rw rw rw
implementation.
implementation.
implementation.
for a list of abbreviations used in register descriptions.
24 23 22 21
WAVE2[1:0] TSEL2[3] TSEL2[2] TSEL2[1] TSEL2[0]
rw rw rw rw
8 7 6 5
WAVE1[1:0] TSEL1[3] TSEL1[2] TSEL1[1] TSEL1[0]
rw rw rw rw
RM0444 Rev 5
20 19 18
rw rw rw
4 3 2
rw rw rw
Section 16.3: DAC
Section 16.3: DAC
Section 16.3: DAC
RM0444
17 16
TEN2 EN2
rw rw
1 0
TEN1 EN1
rw rw