Tim15 Control Register 2 (Tim15_Cr2) - ST STM32G0 1 Series Reference Manual

General-purpose timers (TIM15/TIM16/TIM17)
Bit 2 URS: Update request source
Bit 1 UDIS: Update disable
Bit 0 CEN: Counter enable
Note: External clock and gated mode can work only if the CEN bit has been previously set by
25.5.2

TIM15 control register 2 (TIM15_CR2)

Address offset: 0x04
Reset value: 0x0000
15 14 13
Res. Res. Res. Res.
Bits 15:11 Reserved, must be kept at reset value.
Bit 10 OIS2: Output idle state 2 (OC2 output)
0: OC2=0 when MOE=0
1: OC2=1 when MOE=0
Note: This bit cannot be modified as long as LOCK level 1, 2 or 3 has been programmed
Bit 9 OIS1N: Output Idle state 1 (OC1N output)
0: OC1N=0 after a dead-time when MOE=0
1: OC1N=1 after a dead-time when MOE=0
Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed
Bit 8 OIS1: Output Idle state 1 (OC1 output)
0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0
Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed
782/1390
This bit is set and cleared by software to select the UEV event sources.
0: Any of the following events generate an update interrupt if enabled. These events can be:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
1: Only counter overflow/underflow generates an update interrupt if enabled
This bit is set and cleared by software to enable/disable UEV event generation.
0: UEV enabled. The Update (UEV) event is generated by one of the following events:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
Buffered registers are then loaded with their preload values.
1: UEV disabled. The Update event is not generated, shadow registers keep their value
(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is
set or if a hardware reset is received from the slave mode controller.
0: Counter disabled
1: Counter enabled
software. However trigger mode can set the CEN bit automatically by hardware.
12 11 10 9
Res. OIS2 OIS1N
rw rw
(LOCK bits in the TIM15_BDTR register).
(LOCK bits in TIM15_BDTR register).
(LOCK bits in TIM15_BDTR register).
8 7 6
OIS1 TI1S MMS[2:0]
rw rw rw
RM0444 Rev 5
5 4 3 2
CCDS CCUS
rw rw rw rw
RM0444
1 0
Res. CCPC
rw