Power Control Register 4 (Pwr_Cr4) - ST STM32G0 1 Series Reference Manual

RM0444
Bit 4 EWUP5: Enable WKUP5 wakeup pin
Bit 3 EWUP4: Enable WKUP4 wakeup pin
Bit 2 EWUP3: Enable WKUP3 wakeup pin
Bit 1 EWUP2: Enable WKUP2 wakeup pin
Bit 0 EWUP1: Enable WKUP1 wakeup pin
4.4.4

Power control register 4 (PWR_CR4)

Address offset: 0x0C
Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with
the PWRRST bit in the
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:10 Reserved, must be kept at reset value.
Bit 9 VBRS: V
Bit 8 VBE: V
Bits 7:6 Reserved, must be kept at reset value.
When this bit is set, the WKUP5 external wakeup pin is enabled and triggers a wakeup from
Standby or Shutdown mode when a rising or a falling edge occurs.The active edge is
configured via the WP5 bit in the PWR_CR4 register.
When this bit is set, the WKUP4 external wakeup pin is enabled and triggers a wakeup from
Standby or Shutdown mode when a rising or a falling edge occurs. The active edge is
configured via the WP4 bit in the PWR_CR4 register.
When this bit is set, the WKUP3 external wakeup pin is enabled and triggers a wakeup from
Standby or Shutdown mode when a rising or a falling edge occurs. The active edge is
configured via the WP3 bit of the PWR_CR4 register.
When this bit is set, the WKUP2 external wakeup pin is enabled and triggers a wakeup from
Standby or Shutdown mode when a rising or a falling edge occurs. The active edge is
configured via the WP2 bit of the PWR_CR4 register.
When this bit is set, the WKUP1 external wakeup pin is enabled and triggers a wakeup from
Standby or Shutdown mode when a rising or a falling edge occurs. The active edge is
configured via the WP1 bit of the PWR_CR4 register.
APB peripheral reset register 1
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. VBRS
rw
battery charging resistor selection
BAT
0: 5 kΩ
1: 1.5 kΩ
battery charging enable
BAT
0: Disable
1: Enable
24 23 22
Res. Res. Res.
8 7 6
VBE Res. Res.
rw
RM0444 Rev 5
Power control (PWR)
(RCC_APBRSTR1).
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
WP6 WP5 WP4 WP3
rw rw rw rw
17 16
Res. Res.
1 0
WP2 WP1
rw rw
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