I2C Implementation; I2C Functional Description; Table 161. Stm32G0X1 I2C Implementation - ST STM32G0 1 Series Reference Manual

Inter-integrated circuit (I2C) interface
The following additional features are also available depending on the product
implementation (see
•
SMBus specification rev 3.0 compatibility:
–
–
–
–
–
–
• PMBus rev 1.3 standard compatibility
•
Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming
•
Wakeup from Stop mode on address match.
32.3

I2C implementation

The devices incorporate up to three I²C-bus controllers, I2C1, I2C2, and I2C3, with full or
limited feature sets as shown in the following table.
7-bit addressing mode
10-bit addressing mode
Standard mode (up to 100 kbit/s)
Fast mode (up to 400 kbit/s)
Fast-mode Plus with 20mA output drive I/Os (up
to 1 Mbit/s)
Independent clock
Wakeup from Stop mode
SMBus/PMbus
1. X = supported.
2. Applies to STM32G0B1xx and STM32G0C1xx devices only.
32.4

I2C functional description

In addition to receiving and transmitting data, this interface converts it from serial to parallel
format and vice versa. The interrupts are enabled or disabled by software. The interface is
connected to the I
with a standard (up to 100 kHz), Fast-mode (up to 400 kHz) or Fast-mode Plus (up to
1 MHz) I
This interface can also be connected to a SMBus with the data pin (SDA) and clock pin
(SCL).
928/1390
Section 32.3: I2C
Hardware PEC (Packet Error Checking) generation and verification with ACK
control
Command and data acknowledge control
Address resolution protocol (ARP) support
Host and Device support
SMBus alert
Timeouts and idle condition detection

Table 161. STM32G0x1 I2C implementation

(1)
I2C features
2
C bus by a data pin (SDA) and by a clock pin (SCL). It can be connected
2
C bus.
implementation):
I2C1
X
X
X
X
X
X
X
X
RM0444 Rev 5
RM0444
(2)
I2C2 I2C3
X X
X X
X X
X X
X X
(2)
X / - -
(2)
X / - -
(2)
X / - -