Rtc Shift Control Register (Rtc_Shiftr) - ST STM32G0 1 Series Reference Manual

Real-time clock (RTC)
Bit 13 CALW16: Use a 16-second calibration cycle period
Note: CALM[0] is stuck at 0 when CALW16 = 1. Refer to
Bits 12:9 Reserved, must be kept at reset value.
Bits 8:0 CALM[8:0]: Calibration minus
30.6.10

RTC shift control register (RTC_SHIFTR)

This register is write protected. The write access procedure is described in
write protection on page
Address offset: 0x2C
Backup domain reset value: 0x0000 0000
System reset: not affected
31 30 29
ADD1S Res. Res. Res.
w
15 14 13
Res.
w w
Bit 31 ADD1S: Add one second
Bits 30:15 Reserved, must be kept at reset value.
Bits 14:0 SUBFS[14:0]: Subtract a fraction of a second
Note: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF = 1 to be
900/1390
When CALW16 is set to 1, the 16-second calibration cycle period is selected. This bit must
not be set to 1 if CALW8 = 1.
calibration.
The frequency of the calendar is reduced by masking CALM out of 2
seconds if the input frequency is 32768 Hz). This decreases the frequency of the calendar
with a resolution of 0.9537 ppm.
To increase the frequency of the calendar, this feature should be used in conjunction with
CALP. See Section 30.3.13: RTC smooth digital calibration on page
881.
28 27 26 25
Res. Res. Res.
12 11 10 9
w w w w
0: No effect
1: Add one second to the clock/calendar
This bit is write only and is always read as zero. Writing to this bit has no effect when a shift
operation is pending (when SHPF = 1, in RTC_ICSR).
This function is intended to be used with SUBFS (see description below) in order to
effectively add a fraction of a second to the clock in an atomic operation.
These bits are write only and is always read as zero. Writing to this bit has no effect when a
shift operation is pending (when SHPF = 1, in RTC_ICSR).
The value which is written to SUBFS is added to the synchronous prescaler counter. Since
this counter counts down, this operation effectively subtracts from (delays) the clock by:
Delay (seconds) = SUBFS / (PREDIV_S + 1)
A fraction of a second can effectively be added to the clock (advancing the clock) when the
ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by:
Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))).
sure that the shadow registers have been updated with the shifted time.
24 23 22
Res. Res. Res.
8 7 6
SUBFS[14:0]
w w w
RM0444 Rev 5
Section 30.3.13: RTC smooth digital
20
RTCCLK pulses (32
885.
RTC register
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
w w w w
RM0444
17 16
Res. Res.
1 0
w w