Figure 99. Dma Transfer Of A 128-Bit Data Block During Input Phase; Figure 100. Dma Transfer Of A 128-Bit Data Block During Output Phase - ST STM32G0 1 Series Reference Manual

AES hardware accelerator (AES)
DMA transfer must not include the last block. For details, refer to
procedure to perform a cipher

Figure 99. DMA transfer of a 128-bit data block during input phase

Word3
DIN[127:96]
D127
MSB
DMA
DMA req N
single write
1
(No swapping)
1
I127
MSB
1 4
Order of write to AES_DINR
Data output using DMA
Setting the DMAOUTEN bit of the AES_CR register enables DMA reading from AES. The
AES peripheral then initiates a DMA request during the Output phase each time it requires
to read a 128-bit block (quadruple word) to the AES_DINR register, as shown in
Note: According to the message size, extra bytes might need to be discarded by application in the
last block.

Figure 100. DMA transfer of a 128-bit data block during output phase

Word3
DOUT[127:96]
D127
MSB
DMA
DMA req N
single read
1
(No swapping)
1
O127
MSB
1 4
Order of read from AES_DOUTR
DMA operation in different operating modes
DMA operations are usable when Mode 1 (encryption) or Mode 3 (decryption) are selected
via the MODE[1:0] bitfield of the register AES_CR. As in Mode 2 (key derivation) the
AES_KEYRx registers must be written by software, enabling the DMA transfer through the
DMAINEN and DMAOUTEN bits of the AES_CR register have no effect in that mode.
DMA single requests are generated by AES until it is disabled. So, after the data output
phase at the end of processing of a 128-bit data block, AES switches automatically to a new
data input phase for the next data block, if any.
508/1390
operation.
Chronological order
Increasing address
Memory accessed through DMA
Word2
DIN[95:64]
D96 D95
DMA
DMA req N+1
single write
2
2
AES core input buffer
I96 I95
Chronological order
Increasing address
Memory accessed through DMA
Word2
DOUT[95:64]
D96 D95
DMA
DMA req N+1
single read
2
2
AES core output buffer
O96 O95
Word1
DIN[63:32]
D64 D63
DMA
DMA req N+2
single write
3
AES_DINR
3
I64 I63
Word1
DOUT[63:32]
D64 D63
DMA
DMA req N+2
single read
3
AES_DOUTR
3
O64 O63
RM0444 Rev 5
Section 20.4.4: AES
Word0
DIN[31:0]
D32 D31
DMA
DMA req N+3
single write
4
4
I32 I31
Word0
DOUT[31:0]
D31
D32
DMA
DMA req N+3
single read
4
4
O32 O31
RM0444
D0
LSB
I0
LSB
MSv42160V1
Figure 100.
D0
LSB
O0
LSB
MSv42161V1