Dmamux Request Line Multiplexer Interrupt Channel Status Register; (Dmamux_Csr); Dmamux Request Line Multiplexer Interrupt Clear Flag Register; (Dmamux_Cfr) - ST STM32G0 1 Series Reference Manual

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Bit 7 Reserved, must be kept at reset value.

Bits 6:0 DMAREQ_ID[6:0]: DMA request identification

Selects the input DMA request. See the DMAMUX table about assignments of multiplexer

inputs to resources.

DMAMUX request line multiplexer interrupt channel status register

Address offset: 0x080

Reset value: 0x0000 0000

Bits 31:12 Reserved, must be kept at reset value.

Bits 11:0 SOF[11:0]: Synchronization overrun event flag

The flag is set when a synchronization event occurs on a DMA request line multiplexer

channel x, while the DMA request counter value is lower than NBREQ.

The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register.

Address offset: 0x084

Reset value: 0x0000 0000

Bits 31:12 Reserved, must be kept at reset value.

Bits 11:0 CSOF[11:0]: Clear synchronization overrun event flag

Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR

RM0444 Rev 5

DMA request multiplexer (DMAMUX)

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