Run Mode; Low-Power Run Mode (Lp Run) - ST STM32G0 1 Series Reference Manual

RM0444
Debug mode
By default, the debug connection is lost if the user application puts the MCU in Stop 0,
Stop1, Shutdown, or Standby mode while the debug features are used. This is due to the
fact that the Cortex
However, by setting some configuration bits in the DBGMCU_CR register, the software can
be debugged even when using the low-power modes extensively. For more details, refer to
Section 40.9.1: Debug support for low-power
4.3.1

Run mode

Slowing down system clocks
In Run mode, the speed of the system clocks (SYSCLK, HCLK, PCLK) can be reduced by
programming the prescaler registers. These prescalers can also be used to slow down the
peripherals before entering Sleep mode.
For more details, refer to
Peripheral clock gating
In Run mode, the HCLK and PCLK for individual peripherals and memories can be stopped
at any time to reduce the power consumption.
To further reduce the power consumption in Sleep mode, the peripheral clocks can be
disabled prior to executing the WFI or WFE instructions.
The peripheral clock gating is controlled by the RCC_AHBENR and RCC_APBENRx
registers.
Disabling the peripherals clocks in Sleep mode can be performed automatically by resetting
the corresponding bit in the RCC_AHBSMENR and RCC_APBSMENRx registers.
4.3.2

Low-power run mode (LP run)

To further reduce the consumption when the system is in Run mode, the regulator can be
configured in low-power mode. In this mode, the system frequency should not exceed
2 MHz.
Refer to the product datasheet for more details on voltage regulator and peripherals
operating conditions.
I/O states in Low-power run mode
In Low-power run mode, all I/O pins keep the same state as in Run mode.
Entering Low-power run mode
To enter Low-power run mode, proceed as follows:
1. Optional: Jump into the SRAM and power-down the Flash memory by setting the
FPD_LPRUN bit in the
2. Decrease the system clock frequency below 2 MHz.
3. Force the regulator in low-power mode by setting the LPR bit in the PWR_CR1 register.
Refer to
®
-M0+ core is no longer clocked.
Section 5.4.3: Clock configuration register
Power control register 1
Table 27: Low-power run
modes.
(PWR_CR1).
on how to enter Low-power run mode.
RM0444 Rev 5
Power control (PWR)
(RCC_CFGR).
131/1390
159