Figure 98. 128-Bit Block Construction With Respect To Data Swap - ST STM32G0 1 Series Reference Manual

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AES hardware accelerator (AES)

Figure 98. 128-bit block construction with respect to data swap

DATATYPE[1:0] = 00: no swapping

DATATYPE[1:0] = 01: 16-bit (half-word) swapping

DATATYPE[1:0] = 10: 8-bit (byte) swapping

D119..112 D127..120

DATATYPE[1:0] = 11: bit swapping

D127 D126 D125

D98 D97 D96 D95 D94 D93

AES input/output data block in memory

AES core input/output buffer data

Zero padding (example)

The data in AES key registers (AES_KEYRx) and initialization registers (AES_IVRx) are not

sensitive to the swap mode selection.

Data padding

zeroed bits after the data swap form a contiguous zone at the MSB end of the AES core

input buffer. The example shows the padding of an input data block containing:

48 message bits, with DATATYPE[1:0] = 01

56 message bits, with DATATYPE[1:0] = 10

34 message bits, with DATATYPE[1:0] = 11

D66 D65 D64 D63 D62 D61

also gives an example of memory data block padding with zeros such that the

increasing memory address

most significant bit (127) of memory data block / AEC core buffer

least significant bit (0) of memory data block / AEC core buffer

Order of write to AES_DINR / read from AES_DOUTR

input/output data bit 'x'

RM0444 Rev 5

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