Clock Selection; Figure 180. Counter Timing Diagram, Update Event With Arpe=1 (Counter Overflow) - ST STM32G0 1 Series Reference Manual

RM0444

Figure 180. Counter timing diagram, Update event with ARPE=1 (counter overflow)

Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag
Auto-reload preload
Auto-reload active
22.3.3

Clock selection

The counter clock can be provided by the following clock sources:
•
Internal clock (CK_INT)
•
External clock mode1: external input pin (TIx)
•
External clock mode2: external trigger input (ETR)
•
Internal trigger inputs (ITRx): using one timer as prescaler for another timer, for
example, Timer X can be configured to act as a prescaler for Timer Y. Refer to
one timer as prescaler for another timer on page 664
Internal clock source (CK_INT)
If the slave mode controller is disabled (SMS=000 in the TIMx_SMCR register), then the
CEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual
control bits and can be changed only by software (except UG which remains cleared
automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal
clock CK_INT.
Figure 181
without prescaler.
CK_PSC
CEN
F7
(UIF)
FD
register
Write a new value in TIMx_ARR
register
shows the behavior of the control circuit and the upcounter in normal mode,
RM0444 Rev 5
General-purpose timers (TIM2/TIM3/TIM4)
36
F8 F9 FA FB FC
FD
34 31 30 2F
35 33 32
36
36
for more details.
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: Using
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