Rng Interrupts; Rng Processing Time; Rng Entropy Source Validation; Introduction - ST STM32G0 1 Series Reference Manual

RM0444
19.4

RNG interrupts

In the RNG an interrupt can be produced on the following events:
•
Data ready flag
• Seed error, see
•
Clock error, see
Dedicated interrupt enable control bits are available as shown in
Interrupt acronym
RNG
The user can enable or disable the above interrupt sources individually by changing the
mask bits or the general interrupt control bit IE in the RNG_CR register. The status of the
individual interrupt sources can be read from the RNG_SR register.
Note: Interrupts are generated only when RNG is enabled.
19.5

RNG processing time

The conditioning stage can produce four 32-bit random numbers every 16x
cycles, if the value is higher than 213 cycles (213 cycles otherwise).
More time is needed for the first set of random numbers after the device exits reset (see
Section 19.3.4: RNG
data is first available after either:
•
128 RNG clock cycles + 426 AHB cycles, if f
•
192 RNG clock cycles + 213 AHB cycles, if f
With f
threshold
19.6

RNG entropy source validation

19.6.1

Introduction

In order to assess the amount of entropy available from the RNG, STMicroelectronics has
tested the peripheral using German BSI AIS-31 statistical tests (T0 to T8). The results can
be provided on demand or the customer can reproduce the tests.
19.6.2

Validation conditions

STMicroelectronics has tested the RNG true random number generator in the following
conditions:
•
RNG clock rng_clk= 48 MHz (CED bit = '0' in RNG_CR register) and rng_clk = 400 kHz
(CED bit = '1' in RNG_CR register).
Section 19.3.7: Error management
Section 19.3.7: Error management

Table 100. RNG interrupt requests

Interrupt event Event flag
Data ready flag
Seed error flag
Clock error flag
initialization). Indeed, after enabling the RNG for the first time, random
= (213 x f )/ 64
RNG
True random number generator (RNG)
Enable control bit
DRDY IE
SEIS IE
CEIS IE
< f
AHB
≥ f
AHB
RM0444 Rev 5
Table 100.
Interrupt clear method
None (automatic)
Write 0 to SEIS
Write 0 to CEIS
f
AHB
------------
f
RNG
threshold
threshold
clock
467/1390
472