Adc Registers; Adc Interrupt And Status Register (Adc_Isr) - ST STM32G0 1 Series Reference Manual

RM0444
15.12

ADC registers

Refer to
15.12.1

ADC interrupt and status register (ADC_ISR)

Address offset: 0x00
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. CCRDY Res.
rc_w1
Bits 31:14 Reserved, must be kept at reset value.
Bit 13 CCRDY: Channel Configuration Ready flag
This flag bit is set by hardware when the channel configuration is applied after programming to
ADC_CHSELR register or changing CHSELRMOD or SCANDIR. It is cleared by software by
programming it to it.
0: Channel configuration update not applied.
1: Channel configuration update is applied.
Note: When the software configures the channels (by programming ADC_CHSELR or changing
CHSELRMOD or SCANDIR), it must wait until the CCRDY flag rises before configuring again
or starting conversions, otherwise the new configuration (or the START bit) is ignored. Once the
flag is asserted, if the software needs to configure again the channels, it must clear the CCRDY
flag before proceeding with a new configuration.
Bit 12 Reserved, must be kept at reset value.
Bit 11 EOCAL: End Of Calibration flag
This bit is set by hardware when calibration is complete. It is cleared by software writing 1 to it.
0: Calibration is not complete
1: Calibration is complete
Bit 10 Reserved, must be kept at reset value.
Bit 9 AWD3: Analog watchdog 3 flag
This bit is set by hardware when the converted voltage crosses the values programmed in
ADC_AWD3TR and ADC_AWD3TR registers. It is cleared by software by programming it to 1.
0: No analog watchdog event occurred (or the flag event was already acknowledged and cleared by
software)
1: Analog watchdog event occurred
Bit 8 AWD2: Analog watchdog 2 flag
This bit is set by hardware when the converted voltage crosses the values programmed in
ADC_AWD2TR and ADC_AWD2TR registers. It is cleared by software programming it it.
0: No analog watchdog event occurred (or the flag event was already acknowledged and cleared by
software)
1: Analog watchdog event occurred
Section 1.2 for a list of abbreviations used in register descriptions.
28 27 26 25
Res. Res. Res.
12 11 10 9
EOCAL Res. AWD3
rc_w1 rc_w1
24 23 22 21
Res. Res. Res. Res.
8 7 6
AWD2 AWD1 Res. Res.
rc_w1 rc_w1
RM0444 Rev 5
Analog-to-digital converter (ADC)
20 19 18
Res. Res. Res.
5 4 3 2
OVR EOS EOC
rc_w1 rc_w1 rc_w1
17 16
Res. Res.
1 0
EOSMP ADRDY
rc_w1 rc_w1
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