Tim15 Status Register (Tim15_Sr) - ST STM32G0 1 Series Reference Manual

General-purpose timers (TIM15/TIM16/TIM17)
Bits 12:11 Reserved, must be kept at reset value.
Bit 10 CC2DE: Capture/Compare 2 DMA request enable
0: CC2 DMA request disabled
1: CC2 DMA request enabled
Bit 9 CC1DE: Capture/Compare 1 DMA request enable
0: CC1 DMA request disabled
1: CC1 DMA request enabled
Bit 8 UDE: Update DMA request enable
0: Update DMA request disabled
1: Update DMA request enabled
Bit 7 BIE: Break interrupt enable
0: Break interrupt disabled
1: Break interrupt enabled
Bit 6 TIE: Trigger interrupt enable
0: Trigger interrupt disabled
1: Trigger interrupt enabled
Bit 5 COMIE: COM interrupt enable
0: COM interrupt disabled
1: COM interrupt enabled
Bits 4:3 Reserved, must be kept at reset value.
Bit 2 CC2IE: Capture/Compare 2 interrupt enable
0: CC2 interrupt disabled
1: CC2 interrupt enabled
Bit 1 CC1IE: Capture/Compare 1 interrupt enable
0: CC1 interrupt disabled
1: CC1 interrupt enabled
Bit 0 UIE: Update interrupt enable
0: Update interrupt disabled
1: Update interrupt enabled
25.5.5

TIM15 status register (TIM15_SR)

Address offset: 0x10
Reset value: 0x0000
15 14 13
Res. Res. Res. Res.
786/1390
12 11 10 9
Res. CC2OF CC1OF
rc_w0 rc_w0
8 7 6
Res. BIF TIF COMIF
rc_w0 rc_w0 rc_w0
RM0444 Rev 5
5 4 3 2
Res. Res. CC2IF
rc_w0
RM0444
1 0
CC1IF UIF
rc_w0 rc_w0