Description Of Analog Watchdog 2 And 3; Adc_Awdx_Out Output Signal Generation; Table 75. Analog Watchdog 1 Channel Selection - ST STM32G0 1 Series Reference Manual

Analog-to-digital converter (ADC)
Channels guarded by the analog watchdog
None
All channels
(1)
Single
1. Selected by the AWD1CH[4:0] bits
15.7.2

Description of analog watchdog 2 and 3

The second and third analog watchdogs are more flexible and can guard several selected
channels by programming the AWDxCHy in ADC_AWDxCR (x = 2, 3).
The corresponding watchdog is enabled when any AWDxCHy bit (x = 2,3) is set in
ADC_AWDxCR register.
When converting data with a resolution of less than 12 bits (configured through DRES[1:0]
bits), the LSB of the programmed thresholds must be kept cleared because the internal
comparison is always performed on the full 12-bit raw converted data (left aligned).
Table 74
The AWD2/3 analog watchdog status bit is set if the analog voltage converted by the ADC is
below a low threshold or above a high threshold. These thresholds are programmed in
HTx[11:0] and LTx[11:0] of ADC_AWDxTR registers (x = 2 or 3). An interrupt can be
enabled by setting the AWDxIE bit in the ADC_IER register.
The AWD2 and ADW3 flags are cleared by software by programming them to 1.
15.7.3

ADC_AWDx_OUT output signal generation

Each analog watchdog is associated to an internal hardware signal, ADC_AWDx_OUT (x
being the watchdog number) that is directly connected to the ETR input (external trigger) of
some on-chip timers (refer to the timers section for details on how to select the
ADC_AWDx_OUT signal as ETR).
ADC_AWDx_OUT is activated when the associated analog watchdog is enabled:
• ADC_AWDx_OUT is set when a guarded conversion is outside the programmed
thresholds.
•
ADC_AWDx_OUT is reset after the end of the next guarded conversion which is inside
the programmed thresholds. It remains at 1 if the next guarded conversions are still
outside the programmed thresholds.
•
ADC_AWDx_OUT is also reset when disabling the ADC (when setting ADDIS to 1).
Note that stopping conversions (ADSTP set to 1), might clear the ADC_AWDx_OUT
state.
•
ADC_AWDx_OUT state does not change when the ADC converts the none-guarded
channel (see
AWDx flag is set by hardware and reset by software: AWDx flag has no influence on the
generation of ADC_AWDx_OUT (as an example, ADC_AWDx_OUT can toggle while AWDx
flag remains at 1 if the software has not cleared the flag).
The ADC_AWDx_OUT signal is generated by the ADC_CLK domain. This signal can be
generated even the APB clock is stopped.
370/1390

Table 75. Analog watchdog 1 channel selection

channel
describes how the comparison is performed for all the possible resolutions.
Figure 52)
AWD1SGL bit
RM0444 Rev 5
AWD1EN bit
x
0
1
RM0444
0
1
1