Pwr Registers; Power Control Register 1 (Pwr_Cr1) - ST STM32G0 1 Series Reference Manual

RM0444
4.4

PWR registers

The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).
4.4.1

Power control register 1 (PWR_CR1)

Address offset: 0x00
Reset value: 0x0000 0208. This register is reset after wakeup from Standby mode.
31 30 29
Res. Res. Res. Res.
15 14 13
Res. LPR Res. Res.
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Bits 31:15 Reserved, must be kept at reset value.
Bit 14 LPR: Low-power run
Bits 13:11 Reserved, must be kept at reset value.
Bits 10:9 VOS: Voltage scaling range selection
Bit 8 DBP: Disable RTC domain write protection
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 FPD_LPSLP: Flash memory powered down during Low-power sleep mode
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. VOS[1:0]
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When this bit is set, the regulator is switched from main mode (MR) to low-power mode
(LPR).
00: Cannot be written (forbidden by hardware)
01: Range 1
10: Range 2
11: Cannot be written (forbidden by hardware)
In reset state, the RTC and backup registers are protected against parasitic write access.
This bit must be set to enable write access to these registers.
0: Access to RTC and backup registers disabled
1: Access to RTC and backup registers enabled
This bit determines whether the Flash memory is put in power-down mode or remains in idle
mode when the device enters Low-power sleep mode.
0: Flash memory idle
1: Flash memory powered down
24 23 22
Res. Res. Res.
8 7 6
FPD_
DBP Res. Res.
LPSLP
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RM0444 Rev 5
Power control (PWR)
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
FPD_ FPD_
LPRUN STOP
rw rw rw rw
17 16
Res. Res.
1 0
LPMS[2:0]
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