Fdcan Timestamp Counter Value Register (Fdcan_Tscv) - ST STM32G0 1 Series Reference Manual

FD controller area network (FDCAN)
Bits 31:20 Reserved, must be kept at reset value.
Bits 19:16 TCP[3:0]: Timestamp counter prescaler
Configures the timestamp and timeout counters time unit in multiples of CAN bit times
[1 ... 16].
The actual interpretation by the hardware of this value is such that one more than the value
programmed here is used.
In CAN FD mode the internal timestamp counter TCP does not provide a constant time base
due to the different CAN bit times between arbitration phase and data phase. Thus CAN FD
requires an external counter for timestamp generation (TSS = 10).
These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit
0 [INIT] of CCCR register are set to 1.
Bits 15:2 Reserved, must be kept at reset value.
Bits 1:0 TSS[1:0]: Timestamp select
00: Timestamp counter value always 0x0000
01: Timestamp counter value incremented according to TCP
10: External timestamp counter from TIM3 value (tim3_cnt[0:15])
11: Same as 00.
These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit
0 [INIT] of CCCR register are set to 1.
36.4.9

FDCAN timestamp counter value register (FDCAN_TSCV)

Address offset: 0x0024
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
rc_w rc_w rc_w rc_w
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 TSC[15:0]: Timestamp counter
The internal/external timestamp counter value is captured on start of frame (both Rx and Tx).
When TSCC[TSS] = 01, the timestamp counter is incremented in multiples of CAN bit times
[1 ... 16] depending on the configuration of TSCC[TCP]. A wrap around sets interrupt flag
IR[TSW]. Write access resets the counter to 0.
When TSCC.TSS = 10, TSC reflects the external timestamp counter value. A write access
has no impact.
Note: A "wrap around" is a change of the Timestamp Counter value from non-0 to 0 that is not
caused by write access to TSCV.
1234/1390
28 27 26 25
Res. Res. Res.
12 11 10 9
rc_w rc_w rc_w
24 23 22
Res. Res. Res.
8 7 6
TSC[15:0]
rc_w rc_w rc_w
RM0444 Rev 5
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
rc_w rc_w rc_w rc_w
RM0444
17 16
Res. Res.
1 0
rc_w rc_w