Figure 144. Break And Break2 Circuitry Overview - ST STM32G0 1 Series Reference Manual

Advanced-control timer (TIM1)
All sources are ORed before entering the timer BRK or BRK2 inputs, as per
below.
Core Lockup
PVD
RAM parity Error
Double ECC Error
CSS
BKINP
BKIN inputs
from AF
controller
BKCMP1P
COMP1
output
BKCMP2P
COMP2
output
BKCMP3P
COMP3
(1)
output
BK2INP
BKIN2 inputs
from AF
controller
BK2CMP1P
COMP1
output
BK2CMP2P
COMP2
output
BK2CMP3P
COMP3
(1)
output
1. Available on STM32G0B1xx and STM32G0C1xx salestypes only.
Note: An asynchronous (clockless) operation is only guaranteed when the programmable filter is
disabled. If it is enabled, a fail safe clock mode (for example by using the internal PLL and/or
the CSS) must be used to guarantee that break events are handled.
562/1390

Figure 144. Break and Break2 circuitry overview

Lockup LOCK
PVD LOCK
Parity LOCK
ECC LOCK
BKINE
BKCMP1E
BKCMP2E
BKCMP3E
BK2INE
BK2CMP1E
BK2CMP2E
BK2CMP3E
System break requests
BKF[3:0] BKP
Filter
Application break requests
BK2F[3:0] BK2P
Filter
Application break requests
RM0444 Rev 5
Figure 144
SBIF flag
Software break requests: BG
BIF flag
BKE
Software break requests: B2G
B2IF flag
BK2E
RM0444
BRK request
BRK2 request
MSv66283V1