Double-Buffered Endpoints And Usage In Device Mode - ST STM32G0 1 Series Reference Manual

Universal serial bus full-speed host/device interface (USB)
37.5.3

Double-buffered endpoints and usage in Device mode

All different endpoint types defined by the USB standard represent different traffic models,
and describe the typical requirements of different kind of data transfer operations. When
large portions of data are to be transferred between the host PC and the USB function, the
bulk endpoint type is the most suited model. This is because the host schedules bulk
transactions so as to fill all the available bandwidth in the frame, maximizing the actual
transfer rate as long as the USB function is ready to handle a bulk transaction addressed to
it. If the USB function is still busy with the previous transaction when the next one arrives, it
answers with a NAK handshake and the host PC issues the same transaction again until the
USB function is ready to handle it, reducing the actual transfer rate due to the bandwidth
occupied by re-transmissions. For this reason, a dedicated feature called 'double-buffering'
can be used with bulk endpoints.
When 'double-buffering' is activated, data toggle sequencing is used to select, which buffer
is to be used by the USB peripheral to perform the required data transfers, using both
'transmission' and 'reception' packet memory areas to manage buffer swapping on each
successful transaction in order to always have a complete buffer to be used by the
application, while the USB peripheral fills the other one. For example, during an OUT
transaction directed to a 'reception' double-buffered bulk endpoint, while one buffer is being
filled with new data coming from the USB host, the other one is available for the
microcontroller software usage (the same would happen with a 'transmission' double-
buffered bulk endpoint and an IN transaction).
Since the swapped buffer management requires the usage of all 4 buffer description table
locations hosting the address pointer and the length of the allocated memory buffers, the
USB_CHEPnR registers used to implement double-buffered bulk endpoints are forced to be
used as unidirectional ones. Therefore, only one STAT bit pair must be set at a value
different from 00 (DISABLED): STATRX if the double-buffered bulk endpoint is enabled for
reception, STATTX if the double-buffered bulk endpoint is enabled for transmission. In case
it is required to have double-buffered bulk endpoints enabled both for reception and
transmission, two USB_CHEPnR registers must be used.
To exploit the double-buffering feature and reach the highest possible transfer rate, the
endpoint flow control structure, described in previous chapters, has to be modified, in order
to switch the endpoint status to NAK only when a buffer conflict occurs between the USB
peripheral and application software, instead of doing it at the end of each successful
transaction. The memory buffer which is currently being used by the USB peripheral is
defined by the DTOG bit related to the endpoint direction: DTOGRX (bit 14 of
USB_CHEPnR register) for 'reception' double-buffered bulk endpoints or DTOGTX (bit 6 of
USB_CHEPnR register) for 'transmission' double-buffered bulk endpoints. To implement the
new flow control scheme, the USB peripheral should know which packet buffer is currently
in use by the application software, so to be aware of any conflict. Since in the
USB_CHEPnR register, there are two DTOG bits but only one is used by USB peripheral for
data and buffer sequencing (due to the unidirectional constraint required by double-buffering
feature) the other one can be used by the application software to show which buffer it is
currently using. This new buffer flag is called SW_BUF. In the following table the
correspondence between USB_CHEPnR register bits and DTOG/SW_BUF definition is
explained, for the cases of 'transmission' and 'reception' double-buffered bulk endpoints.
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