Apb Peripheral Clock Enable Register 1 (Rcc_Apbenr1) - ST STM32G0 1 Series Reference Manual

Reset and clock control (RCC)
Bit 8 FLASHEN: Flash memory interface clock enable
Bits 7:2 Reserved, must be kept at reset value.
Bit 1 DMA2EN: DMA2 and DMAMUX clock enable
Bit 0 DMA1EN: DMA1 and DMAMUX clock enable
5.4.15

APB peripheral clock enable register 1 (RCC_APBENR1)

Address offset: 0x3C
Reset value: 0x0000 0000
31 30 29 28
LPTIM1 LPTIM2 DAC1 PWR
EN EN EN EN
rw rw rw rw
15 14 13 12
FDCA
SPI3 USB
SPI2
(1) (1)
EN
EN EN
EN
rw rw rw rw
1. Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to
of peripherals.
Bit 31 LPTIM1EN: LPTIM1 clock enable
Bit 30 LPTIM2EN: LPTIM2 clock enable
Bit 29 DAC1EN: DAC1 interface clock enable
198/1390
Set and cleared by software.
0: Disable
1: Enable
This bit can only be cleared when the Flash memory is in power down mode.
Set and cleared by software.
0: Disable
1: Enable
DMAMUX is enabled as long as at least one DMA peripheral is enabled.
Set and cleared by software.
0: Disable
1: Enable
DMAMUX is enabled as long as at least one DMA peripheral is enabled.
27 26 25
DBG UCPD2 UCPD1
EN EN EN
rw rw rw
11 10 9
USART
RTC
WWDG
N 6
APB
EN
(1) (1)
EN
EN
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Set and cleared by software.
0: Disable
1: Enable
Set and cleared by software.
0: Disable
1: Enable
Set and cleared by software.
0: Disable
1: Enable
(1)
24 23 22 21
I2C3
CEC I2C2 I2C1
(1)
EN EN EN
EN
rw rw rw rw
8 7 6 5
USART LP
TIM7
5 UART2
Res.
EN
(1) (1)
EN EN
rw rw rw
RM0444 Rev 5
20 19 18
LP
USART4 USART3
UART1
(1) (1)
EN EN
EN
rw rw rw
4 3 2
TIM6 TIM4
Res.
(1) (1) (1)
EN EN
rw rw
Section 1.4: Availability
RM0444
17 16
CRSE
USART2
(1)
EN
N
rw rw
1 0
TIM3 TIM2
EN EN
rw rw