Smbus Specific Features; Table 170. Examples Of Timings Settings For Fi2Cclk = 48 Mhz - ST STM32G0 1 Series Reference Manual

Inter-integrated circuit (I2C) interface
2. t t minimum value is 4 x t
SYNC1 + SYNC2
3. t t minimum value is 4 x t
SYNC1 + SYNC2
4. t t minimum value is 4 x t
SYNC1 + SYNC2
Table 170. Examples of timings settings for f
Parameter
10 kHz
PRESC
SCLL 0xC7
t 200 x 250 ns = 50 µs
SCLL
SCLH 0xC3
t 196 x 250 ns = 49 µs
SCLH
(1)
t ~100 µs
SCL
SDADEL
t 2 x 250 ns = 500 ns
SDADEL
SCLDEL
t 5 x 250 ns = 1250 ns
SCLDEL
1. The SCL period t is greater than t
SCL
examples.
2. t t minimum value is 4x t
SYNC1 + SYNC2
3. t t minimum value is 4x t
SYNC1 + SYNC2
4. t t minimum value is 4x t
SYNC1 + SYNC2
32.4.12

SMBus specific features

This section is relevant only when SMBus feature is supported. Refer to
implementation.
Introduction
The System Management Bus (SMBus) is a two-wire interface through which various
devices can communicate with each other and with the rest of the system. It is based on I
principles of operation. SMBus provides a control bus for system and power management
related tasks.
This peripheral is compatible with the SMBus specification (http://smbus.org).
The System Management Bus Specification refers to three types of devices.
•
A slave is a device that receives or responds to a command.
•
A master is a device that issues commands, generates the clocks and terminates the
transfer.
•
A host is a specialized master that provides the main interface to the system's CPU. A
host must be a master-slave and must support the SMBus host notify protocol. Only
one host is allowed in a system.
This peripheral can be configured as master or slave device, and also as a host.
962/1390
= 250 ns. Example with t
I2CCLK
= 250 ns. Example with t
I2CCLK
= 250 ns. Example with t
I2CCLK
Standard-mode (Sm)
100 kHz
0xB
20 x 250 ns = 5.0 µs
16 x 250 ns = 4.0 µs
(2)
~10 µs
0x2
2 x 250 ns = 500 ns
0x4
5 x 250 ns = 1250 ns
+ t
SCLL SCLH
= 83.3 ns. Example with t
I2CCLK
= 83.3 ns. Example with t
I2CCLK
= 83.3 ns. Example with t
I2CCLK
SYNC1 +
SYNC1 +
SYNC1 +
Fast-mode (Fm)
0xB 5
0x13 0x9
10 x 125 ns = 1250 ns
0xF 0x3
4 x 125 ns = 500 ns
(2)
~2500 ns
0x2 0x3
3 x 125 ns = 375 ns
0x4 0x3
4 x 125 ns = 500 ns
due to the SCL internal detection delay. Values provided for t
SYNC1 +
SYNC1 +
SYNC1 +
RM0444 Rev 5
t = 1000 ns.
SYNC2
t = 750 ns.
SYNC2
t = 500 ns.
SYNC2
= 48 MHz
I2CCLK
Fast-mode Plus (Fm+)
400 kHz
5
0x3
4 x 125 ns = 500 ns
0x1
2 x 125 ns = 250 ns
(3)
~875 ns
0x0
0 ns
0x1
2 x 125 ns = 250 ns
t = 1000 ns
SYNC2
t = 750 ns
SYNC2
t = 250 ns
SYNC2
Section 32.3: I2C
RM0444
1000 kHz
(4)
are only
SCL
2
C