Figure 88. Ecb/Cbc Decryption (Mode 3) - ST STM32G0 1 Series Reference Manual

AES hardware accelerator (AES)
register to 000 or 001, respectively. Data type can also be defined, using
DATATYPE[1:0] bitfield. KEYSIZE bitfield must be kept as-is.
3. Write the AES_IVRx registers with the initialization vector (required in CBC mode only).
4. Enable AES by setting the EN bit of the AES_CR register.
5. Write the AES_DINR register four times to input the cipher text (MSB first), as shown in
Figure
6. Wait until the CCF flag is set in the AES_SR register.
7. Read the AES_DOUTR register four times to get the plain text (MSB first), as shown in
Figure
8. Repeat steps
WR
CT3
MSB
4 write operations into
AES_DINR[31:0]
PT = plaintext = 4 words (PT3, ... , PT0)
CT = ciphertext = 4 words (CT3, ... , CT0)
Suspend/resume operations in ECB/CBC modes
To suspend the processing of a message, proceed as follows:
1. If DMA is used, stop the AES DMA transfers to the IN FIFO by clearing the DMAINEN
bit of the AES_CR register.
2. If DMA is not used, read four times the AES_DOUTR register to save the last
processed block. If DMA is used, wait until the CCF flag is set in the AES_SR register
then stop the DMA transfers from the OUT FIFO by clearing the DMAOUTEN bit of the
AES_CR register.
3. If DMA is not used, poll the CCF flag of the AES_SR register until it becomes 1
(computation completed).
4. Clear the CCF flag by setting the CCFC bit of the AES_CR register.
5. Save initialization vector registers (only required in CBC mode as AES_IVRx registers
are altered during the data processing).
6. Disable the AES peripheral by clearing the bit EN of the AES_CR register.
7. Save the AES_CR register and clear the key registers if they are not needed, to
process the higher priority message.
8. If DMA is used, save the DMA controller status (pointers for IN and OUT data transfers,
number of remaining bytes, and so on).
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88.
88. Then clear the CCF flag by setting the CCFC bit of the AES_CR register.
5-6-7 to process all the blocks encrypted with the same key.

Figure 88. ECB/CBC decryption (Mode 3)

WR WR WR
CT2 CT1 CT0
LSB
Input phase
Wait until flag CCF = 1
Computation phase
RM0444 Rev 5
RM0444
RD RD RD RD
PT3 PT2 PT1 PT0
MSB LSB
Output phase
4 read operations from
AES_DOUTR[31:0]
MS18938V3